Aldec Design and Verification Blog Trending Articles SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO Enabling TySOM Zynq-based Embedded Development Board for AWS IoT Greengrass Connecting Emulated Design to External PCI Express Device Is your Verification plan pulling you in multiple directions? Try FSM Coverage How to Develop a 4K Ultra High Definition Image/Video Processing Application Using Zynq® MPSoC FPGA ARM-based SoC Co-Emulation using Zynq Boards All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Aldec Engineers: Taking Action and Giving Back as a Team The Annual Katowice Business Run For engineers, the importance of keeping active cannot be understated. When thousands of hours are spent seated in front of monitors, healthy activities such as running are more than fun... they are necessary. At Aldec, our team... Tags:Training Like(2) Comments (0) Read more The 80s music at DAC was my idea. You're welcome. DAC Chats to be presented live online If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” - that would be me. A few weeks before DAC... Tags:Embedded,OS-VVM,safety-critical,Training,UVM,Verification Like(2) Comments (0) Read more HW Designers: Brush up on your SV with Online Training Fast Track to SystemVerilog for Verilog Users The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and ... Tags:Design,Simulation,SystemVerilog,Training,Verification,Verilog Like(0) Comments (0) Read more Back from DAC Functional Verification Insights from Austin I just returned back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.... Tags:Functional Verification,Mixed-signal,SoC,SystemVerilog,Training,Verification,Verilog Like(2) Comments (0) Read more
