Xilinx Opens Their IP for Simulation with Aldec Flow

Using P1735 Interoperable Encryption Standard

Mariusz Grabowski, FPGA Design and Verification Engineer
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As we know, the first industry standard trying to solve the Intellectual Property (IP) delivery problem was Verilog-2005. It contained sound theoretical description but lacked some practical usage guidelines needed to create interoperable implementations. VHDL-2008 standard, based on the same donation by Cadence Design Systems, provided some clarifications but did not address all of the issues. SystemVerilog-2009 approached the ideal, but left quite a few wrinkles affecting interoperability. In other words, there is currently no defined, independent standard for describing IP encryption markup for design information formats. Each design format which incorporates IP encryption describes their markup differently leading to confusing interpretation. Users of those standards also lack a recommended practice for inter-operable use of IP encryption. 

For this reason the IEEE P1735 Working Group (Web Page) began developing the Proposed 1735 (P1735) standard describing an interoperable cryptosystem for safe delivery of IP to be used in VHDL and SystemVerilog design and verification. Creation of the first version of the P1735 (V1) standard in 2011 became an important stage in the inception of a reliable, industry-wide ecosystem to handle IP. With the recent release of Xilinx® Vivado® 2013.1, the EDA industry witnessed another successful application for the P1735 V1 interoperable encryption standard; behavioral simulation of Xilinx IP is now supported for Aldec Active-HDL™ and Riviera-PRO™, Cadence Incisive Enterprise Simulator, Mentor Graphics ModelSim and Questa, and Synopsys VCS. (Related Xilinx document: Vivado Design Suite 2013.1 User Guide).

 

IP vendor can now easily join an ecosystem already supported by all the major vendors and begin delivering P1735 encrypted simulation IP cores.

Refer to the following application note, Interoperable Encryption of HDL Intellectual Property, to learn how easy it is to prepare an interoperable IP; and the related Xilinx document: Vivado Design Suite 2013.1 User Guide.

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).

  • Products:
  • Active-HDL
  • FPGAデザイン・シミュレーション,
  • Riviera-PRO
  • Advanced Verification

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