Documentation Search in Resources Articles Manuals -OR- All Products Active-HDL Riviera-PRO ALINT-PRO HES-DVM HES Proto-AXI HES™ Boards RTAX/RTSX Adaptor Boards HES-DVM Proto Cloud Edition TySOM™ EDK Spec-TRACER DO-254/CTS All Documents Application Notes Manual Demonstration Videos FAQ Recorded Webinars Tutorials White Papers Technical Specification Case Studies All Categories Coverage 3rd Party Integration Design Entry, Documentation Simulation, Debugging Design Management, Libraries Advanced Verification Assertions and Functional Coverage RTL Simulation & Verification HDL Languages Encryption Military & Aerospace Verification Design Rule Checking Design Hardware Emulation Solutions Encryption Design HDL Languages RTL Simulation & Verification Assertions and Functional Coverage Advanced Verification Design Rule Checking Military & Aerospace Verification Hardware Emulation Solutions Tutorials Prototyping High-Level Synthesis Embedded Embedded Embedded High Performance Computer SoC & ASIC Prototyping Reset Results Name Products Type Action Active-HDL Simulator Options in Vivado Active-HDL Application Notes Active-HDL Upgrade Active-HDL FAQ Active-HDL and GOWIN Flow Active-HDL Application Notes Add BDE/ASF generated code to Source Revision Control Active-HDL FAQ Add file for simulation without manually adding the file to design. Active-HDL FAQ Adding to Memory Viewer from Structures Window Active-HDL FAQ Aldec DO-254 Solutions Blueprint The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL Simulator, Synthesis, Place & Route and Static Timing Analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including Requirements Management, Traceability, Tests Management, Design Rule Checker, Clock Domain Crossings (CDC) Analysis, Code Coverage and FPGA Physical Test Systems. Active-HDL, ALINT-PRO, Spec-TRACER, DO-254/CTS White Papers Ambiguous Subprogram Active-HDL FAQ Analog Waveform Display Active-HDL FAQ Assigning Pin Numbers in Block Diagram Editor Active-HDL FAQ Automated ASIC Regressions With Aldec Server Farm Manager Abstract: Aldec's Server Farm Manager (SFM) addresses ASIC regression testing issues for the fast, cost effective and high quality ASIC design verification. Active-HDL White Papers BDE format change: This file was created in a version later than 9.2.2499.4581.01 and it cannot be read in version 9.2.2499.4581.01 Active-HDL FAQ Can I customize my keyboard shortcuts in Active-HDL? Active-HDL FAQ Can I disable the compile time warning messages in the command line? Active-HDL FAQ Can I import an existing schematic developed in Viewlogic into Active-HDL? Active-HDL FAQ Can I use Terminal Services with Active-HDL? Active-HDL FAQ Cannot Debug Source Code. Cannot Set Breakpoints. Active-HDL FAQ Cannot Open Configuration Active-HDL FAQ Cannot Select Top Level Active-HDL FAQ Clarifying Language Methodology Confusion Abstract: Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only adds to the confusion. This document tries to clarify the situation. Active-HDL White Papers ... 291 results (page 2/15)
