Ambiguous Subprogram

Description:

I received the following error during compilation. The compiler complains a VHDL operation is ambiguous. What is worng?

Error: COMP96_0334: <file name>.vhd , Subprogram "<variable name>" is ambiguous> 

Solution:

It seems that you have overloaded functions defined by both the STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR type. You will have to remove the additional, unnecessary subprogram. Note that instead of deleting/commenting out the code block with the offending subprogram, you can use the -vhdl_comp_off -2008 and -vhdl_comp_on pragmas. The pragmas will disable the compilation of the subprogram only in the -2008 mode preserving backwards compatibility with earlier versions of the standard. For more information on the -vhdl_comp_off pragma

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