Port Declaration Orders


Why don't the signals inside blocks on a block diagram (bde) follow the exact same order as representative in the corresponding Verilog/VHDL source code?


Signal order inside the blocks will appear in the same order as in Verilog/VHDL source code for Active-HDL 8.3 and later versions.

Ask Us a Question

Ask Us a Question

Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.