Aldec Design and Verification Blog Trending Articles Bridging Simulation and Hardware Advanced Static Linting for FPGA Performance Optimization Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Synthesis of Energy-Efficient FSMs Implemented in PLD Circuits Finite State Machines in low-power world Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions?... Tags:FPGA,university,Verification Like(2) Comments (0) Read more Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs! Guest Blog by Alex Grove, Applications Specialist at FirstEDA I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices... Tags:Aceleration,ASIC,Embedded,FPGA,Hardware,university,Verification,Xilinx Like(2) Comments (0) Read more Why Digital Design Students choose Active-HDL™ Mixed-language simulation for VHDL-2008, Verilog and SystemVerilog (Design) Active-HDL™ STUDENT EDITION is a popular solution for university students looking to enhance their digital design learning experience. A mixed-language simulator that supports VHDL-2008,... Tags:Design,FPGA,HDL,university Like(2) Comments (0) Read more
