Aldec Design and Verification Blog Trending Articles Bridging Simulation and Hardware Advanced Static Linting for FPGA Performance Optimization Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Register for Aldec Technical Sessions & Demos at DAC 2013 Advanced Verification, HW/SW Emulation, and more This year’s Design Automation Conference (DAC) will be held in Austin, Texas. If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat.... Tags:HES,Functional Verification,FPGA,Design,Emulation,Aceleration,ASIC,SoC Like(1) Comments (0) Read more Aldec in the Classroom Of Today’s Top Engineering Universities Aldec’s University Program is committed to providing future engineers with world-class tools for their digital system designs and verification methodologies. These tools are offered at a lower cost to educational facilities who meet the university program requirements. In addition, students... Tags:Prototyping,Functional Verification,FPGA,Emulation,Aceleration Like(1) Comments (0) Read more
