Aldec in the Classroom

Of Today’s Top Engineering Universities

Bill Jason P. Tomas, Product Engineer, Hardware Division
Like(1)  Comments  (0)

Aldec’s University  Program is committed to providing future engineers with world-class tools for their digital system designs and verification methodologies.  These tools are offered at a lower cost to educational facilities who meet the university program requirements. In addition, students  are able to download the free Active-HDL™ Student Edition which allows them to use the design entry and simulation tool throughout their coursework.


Students and faculty are also provided with access to online resources such as whitepapers, webinars, and demonstrations. Aldec takes pride in its commitment to tomorrow’s engineers, and often sends engineers to deliver onsite presentations to students and faculty on the latest research in the field of system verification. Aldec recently presented as part of the VLSI Design & Test Seminar Series by Auburn University. This series seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems.


Aldec visited Auburn University this past month for a seminar on a paper to be presented during this year’s Military and Aerospace Programmable Logic Devices (MAPLD) conference. The paper titled, “Hybrid Platform for High Capacity FPGA Validation and Verification”, showcases the Hardware Emulation Solution (HES) ecosystem, a complete validation and verification platform for large capacity SoC and ASIC designs.  During the visit, Aldec Research Engineer and Auburn graduate, Bill Jason Tomas, presented different modes of validation and verification including: simulation acceleration, prototyping, and transaction level emulation. Tomas also presented many debugging capabilities of Aldec’s hardware emulation application, HES-DVM™, to quickly debug and diagnose system-level faults occurring in a design.

Tomas also visited digital design classrooms to showcase Aldec’s FPGA design and verification tools, Active-HDL™ and Riviera-PRO™.  In these demonstrations, Tomas utilized examples from classroom activities and displayed how students can utilize Aldec tools to develop, debug, and verify their own digital systems.


“It was a great experience giving back to my alma mater, and providing them with tools which will help them with their studies”, stated Tomas during an interview with faculty.


For more information on attaining Aldec tools for your university or having an Aldec engineer provide in-class demonstrations, contact Aldec or visit

Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies. 


Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.