Webinars, YouTube, Articles... What’s your preference?

Useful resources to help you get ahead

Sunil Sahoo, Corporate Applications Engineer
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“USEFUL” is a word you’ll hear a lot over here at Aldec. It’s the number one way we rank our success when developing a new product or feature.

“How USEFUL is it?” is the most common phrase we challenge one another with when brainstorming new ideas. The idea being that everything we do should be focused on making life easier for our customer – the engineer in the field.

This focus on usefulness applies to educational resources as well. Aldec’s Technical Marketing team is continually developing new training materials and resources – and each and every one must prove itself useful. Based on view metrics from Google analytics and download data, below are some of the materials your fellow engineers found most useful this past year.

Take a look, and then comment below to let us know your thoughts. Webinars, YouTube, Articles, or White Papers, what training material format do you find MOST USEFUL?




High-level thinking: Using Python for rapid verification of VHDL and Verilog design

Presents a methodology that enables rapid verification and integration of RTL designs. Aldec is committed to supporting the design verification community by delivering relevant resources, news and trainings. In this webinar, Chris Higgs, Lead Developer at Potential Ventures, introduces Cocotb, an open-source Python verification framework that is freely available.


Fast Track to Riviera-PRO
Part 1: Design Entry and Simulation
Part 2: Advanced Debugging, Code Coverage and Scripting


Static Design Rule Checks in FPGA Design

Design Rule Checks have traditionally been associated with large ASIC designs, and have been used effectively to catch static violations as early as possible, thereby reducing debug time in the subsequent verification process. The benefits are the same when using DRC in the design methodology of FPGA.


Elemental Analysis: DO-254 Additional Verification for Levels A and B

Appendix B of RTCA DO-254 describes elemental analysis as one of the possible additional verification techniques for Level A and B complex electronic hardware. Code coverage in and of itself does not always satisfy the objectives of DO-254. This presentation provides background on elemental analysis and when code coverage is sufficient for HDL based designs.




Averting Clock-Domain Crossing issues in FPGA Design

A solution to your worst CDC nightmare


Stress-Relief for Requirements-Based Verification

Verification of Safety-Critical FPGAs under Strict DO-254 Guidance


Want to be a Verification Engineer? Practice. Practice. Practice.

Simulate UVM & SystemVerilog online for free


Simulate Smarter than a Secret Agent

Learn how features like Plot Window can save your life







For more on Aldec’s Useful Solutions, visit www.aldec.com/solutions or email sales@aldec.com.

Sunil Sahoo provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions that include Digital Design Engineer Verification Engineer and  Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.

  • Products:
  • Active-HDL
  • FPGAデザイン・シミュレーション,
  • Riviera-PRO
  • アドバンスベリフィケーション,
  • ハードウェア・アシステッド・ベリフィケーション,
  • Spec-TRACER
  • 要件管理,
  • DO-254/CTS
  • FPGAテスト・システム


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