Play WebinarTitle: Bridging Simulation and Hardware: Hardware-in-the-Loop in ActionDescription: Hardware-in-the-Loop (HIL) is a powerful real-time testing methodology that connects physical hardware components to a simulated environment representing the rest of the system. By enabling parts of the system to be replaced with models or simulations, HIL accelerates project validation and helps identify issues earlier in the design cycle. In this webinar, we will present a HIL solution that integrates Riviera-PRO, VUnit™, and a TySOM Zynq™ MPSoC™ FPGA board to streamline automated test execution. Through a live demonstration, we will showcase how AES Cipher designs can be efficiently verified using Aldec’s dedicated USB Bridge IP, which seamlessly links simulation in Riviera-PRO with the programmable logic in the FPGA board. Attendees will also discover how to build scalable verification environments that unify simulation and hardware execution with a single script, significantly reducing effort while improving reliability and repeatability.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
