Resources Search in Resources Articles Manuals -OR- All Products Active-HDL Riviera-PRO ALINT-PRO HES-DVM HES Proto-AXI HES™ Boards RTAX/RTSX Adaptor Boards HES-DVM Proto Cloud Edition TySOM™ EDK Spec-TRACER DO-254/CTS All Documents Application Notes Manual Demonstration Videos FAQ Recorded Webinars Tutorials White Papers Technical Specification Case Studies All Categories Coverage 3rd Party Integration Design Entry, Documentation Simulation, Debugging Design Management, Libraries Advanced Verification Assertions and Functional Coverage RTL Simulation & Verification HDL Languages Encryption Military & Aerospace Verification Design Rule Checking Design Hardware Emulation Solutions Encryption Design HDL Languages RTL Simulation & Verification Assertions and Functional Coverage Advanced Verification Design Rule Checking Military & Aerospace Verification Hardware Emulation Solutions Tutorials Prototyping High-Level Synthesis Embedded Embedded Embedded High Performance Computer SoC & ASIC Prototyping Reset Results Name Products Type Action 01-Creating HDL Text Modules Learn how to create HDL Text Modules in Active-HDL Active-HDL Tutorials 02-Creating HDL Graphical Modules Learn how to create schematic diagram and finite state machine in Active-HDL Active-HDL Tutorials 03-Design Flow Manager Learn how to use Design Flow Manager in Active-HDL Active-HDL Tutorials 04-Creating Testbenches Learn how to create a Testbench in Active-HDL Active-HDL Tutorials 05-Running Simulation Learn how to run simulation and use waveform viewer in Active-HDL Active-HDL Tutorials 06-HDL_Debugging Learn how to use HDL debugging tools in Active-HDL Active-HDL Tutorials 07-Code_Coverage Learn how to use Code Coverage in Active-HDL Active-HDL Tutorials 08-Design_Profiler Learn how to use Design Profiler Active-HDL Tutorials 09-Documentation_Features Learn how to export designs to HTML and PDF in Active-HDL Active-HDL Tutorials 10-Simulink Interface Learn how to use Simulink® Interface in Active-HDL Active-HDL Tutorials 1.1 Basics : Workspace A Workspace is comprised of individual designs containing resources such as source files and output files with simulation results. Learn how to create a new Workspace using the New Workspace Wizard, manage an existing Workspace, and manage the different components of the Workspace. Active-HDL Demonstration Videos 1.2 Basics: Design Flow Manager The Design Flow Manager (DFM) is designed to automate and simplify the design, synthesis, and implementation processes. The interface takes the form of design flowcharts which show the design path in graphical form. Learn how to enable the DFM, choose third party vendor tools for synthesis and implementation, and how to perform each stage of the synthesis and implementation processes. Active-HDL Demonstration Videos 1.3 Basics: Library Manager Learn how to create and manage user libraries, and how to utilize pre-compiled FPGA vendor libraries. Active-HDL Demonstration Videos 2.1 Design Entry: Block Diagram Editor The Block Diagram Editor (BDE) is Active-HDL's tool for graphical entry of VHDL, Verilog, and EDIF designs. This is especially useful to those with HDL designs that are largely structural since it is easier to enter descriptions graphically rather than typing hundreds of source code lines. Learn how to create a new block diagram by adding new ports, adding symbols, editing symbols (pin placement, pin names, etc.), connecting symbols with wires/bus, generate HDL code, and how to create a graphical testbench. Active-HDL Demonstration Videos 2.2 Design Entry: FSM Editor Learn how to create a new Finite State Machine (FSM), define ports, add new states, transitions, actions, and conditions; add multiple state machines, generate HDL code, generate a testbench, and run a simulation to trace over the transitions to observe the functionality of the state machine. Active-HDL Demonstration Videos 2.3 Design Entry: HDL Editor The HDL Editor is a text editor for editing HDL source code. It contains features such as keyword coloring (VHDL, Verilog/SystemVerilog, C/C++, SystemC, OVA, and PSL), recording/playing actions, bookmarks, hyperlinks to files, creating structure groups, breakpoints, autoformat/smart indentation, etc. Learn how to create a new HDL file with the New Design Wizard and how to utilize the HDE features within that created source file. Active-HDL Demonstration Videos 3.1 Compilation and Simulation: Compilation and Simulation Learn how to specify design settings for compilation (setting up debugging windows, selecting maximum optimization, etc.), how to initialize and run simulations, how to view the simulation results, and how to perform compilation and simulation with scripts. Active-HDL Demonstration Videos 3.2 Compilation and Simulation: Compiling Vivado Simulation Libraries When you instantiate any Xilinx black box component in your design, Active-HDL will look for the vendor libraries to define functionality of the Xilinx Component. Before performing simulation of these designs, it is crucial not only to have the proper simulation libraries, but the correct version as well. Active-HDL Demonstration Videos 3.3 Compilation and Simulation: Running Active-HDL in Batch Mode Using vSimSA Active-HDL can be run in the batch mode, that is, without using the graphical user interface (GUI). Active-HDL batch mode is referred to as VSimSA or a stand-alone simulator. The batch mode allows running a comprehensive processing of a design or a set of designs. This video will cover how to access both Interactive Mode and Batch Mode as well as demonstrating some basic commands in the VSimSA shell and OS shell to set libraries, compile files, and run simulation. Active-HDL Demonstration Videos 4.1 Debugging: Introduction to Debugging Active-HDL provides debugging windows such as the Console, Breakpoints, Watch, Process, Call Stack, and List Viewer. Learn how to utilize the features of each window and how to use the windows to debug your designs. Active-HDL Demonstration Videos ... 362 results (page 1/19)
