Resources

The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL Simulator, Synthesis, Place & Route and Static Timing Analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including Requirements Management, Traceability, Tests Management, Design Rule Checker, Clock Domain Crossings (CDC) Analysis, Code Coverage and FPGA Physical Test Systems.

Open Source - VHDL Verification Methodology (OS-VVM™) provides advanced verification capabilities to VHDL teams. Attendees will learn how to add functional coverage, constrained random test, and coverage driven random test to their current testbenches. OS-VVM has a straight-forward usage model that allows the addition of functional coverage, constrained random, and coverage driven random features to a testbench in part or in whole. This webinar demonstrates how the addition of Functional Coverage to testbenches is necessary - even with directed tests. Constrained Random or Coverage Driven randomization can be added when and where needed, and there is even the ability to mix directed, algorithmic, file-based, constrained random, and coverage driven random methods. OS-VVM is open source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations, and has been produced as a joint effort between Aldec and SynthWorks, both companies committed to provide continued support to VHDL design community. Play webinar   

The majority of FPGA designers who are proficient in traditional HDLs might have heard about assertions, but haven’t had time to try them out. Designers should be aware that assertions are quickly becoming standard part of both design and verification process, so learning how to use them is a future necessity. This webinar provides quick and easy introduction to the basic ideas and applications of assertions: sequences, properties, assert and cover commands, etc. Practical examples are used both during presentation and live demonstration in the simulator. Play webinar   

Assertion-based verification (ABV) is the use of assertions for the efficient verification of low-level design specification. These assertions could be verified by simulation and formal verification methods. SystemVerilog Assertions (SVA) standard provides powerful means to express both immediate and concurrent assertions as well as functional coverage constructs. Unlike SystemVerilog, VHDL does not include the concept of concurrent assertions (while VHDL assert statements being similar to immediate assertions in SVA). In this webinar, we will present various methods to implement assertions in VHDL designs as well as identify the strengths and limitations of each method. These methods include PSL (VHDL flavor), the usage of Open Verification Library (OVL) as well as concurrent assertions development using procedural code with assert statements. Play webinar   

Abstract: Aldec's Server Farm Manager (SFM) addresses ASIC regression testing issues for the fast, cost effective and high quality ASIC design verification.

Abstract: Experienced users of VHDL simulation with testbenches appreciate additional layer of safety that Coverage Analysis gives them. But are all kinds of coverage equally beneficial? While Code Coverage is certainly useful, it really verifies quality of the testbench, not the design itself. In this webinar we will show how to improve quality of the design using Property Coverage and Functional Coverage (with help of OS-VVM). Play webinar   

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA verification projects from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either simple or complex FPGA blocks. Looking to improve your VHDL FPGA verification methodology? OSVVM is the right solution. We have all the pieces needed for verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them. This webinar provides a broad overview of OSVVM's capabilities. You will learn the OSVVM way of: > Creating a well-structured, testbench framework > Creating verification components (overview – in Part 2 we will cover details) > Creating test cases > Using AffirmIf for self-checking > Using logs for conditional message printing to facilitate debug > Adding constrained random to your tests > Using scoreboards for self-checking > Adding functional coverage > Using Intelligent Coverage Randomization – randomization using a functional coverage model. > Using Alert to add protocol checks > Test Synchronization and Watchdogs > Test Wide Reporting > Using OSVVM's Simulator Independent Scripting (overview – in Part 3 we will cover details) > Creating Test Reports in HTML for Humans > Creating Test Reports in JUnit XML for Continuous Integration OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that: > Are simple to use and work like built-in language features. > Maximize reuse and reduce project schedule. > Improve readability and reviewability by the whole team including software and system engineers. > Facilitate debug with HTML based test suite and test case reporting. > Support continuous integration (CI/CD) with JUnit XML test suite reporting. > Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering. > Rival the verification capabilities of SystemVerilog + UVM. OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey.  Play webinar   

Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their "Lite" or "Easy" approach. Creating a verification component (VC) using OSVVM is simple enough that neither a "Lite" version nor a script is needed. This presentation is a walk through the steps to write a verification component that effectively utilizes OSVVM capabilities. One big time saver in creating OSVVM's VCs is our Model Independent Transactions (MIT). MIT evolved from the observation that many interfaces do the same sort of transactions. For example, Address Bus Interfaces, such as AXI4, Avalon, and Wishbone, all do read and write operations. Similarly, streaming interfaces, such as AxiStream and UARTs, all do send and get operations. OSVVM defines a pattern, or if you prefer an internal standard, for the Address Bus transaction interface and transaction API. It does the same for Stream Interfaces. The result of using OSVVM's MIT is that a VC developer can focus on writing the VC behavior. This makes OSVVM's VC based approach as simple as a "Lite" approach that codes interface behavior in a subprogram. Starting with a VC allows us to include additional capability – such as protocol and timing checkers. VCs also provide a path to greater capability – such as with an AXI4 interface where the Address Write, Write Data, Write Response, Address Read, and Read Data aspects of the interface are independent of each other and need to be handled by separate processes. With a VC, these capabilities can be incrementally added during the test process. At the end of the day, OSVVM does not need a "Lite" version because we make writing verification components as simple as writing a procedure. Nothing more than a template is needed. Any of OSVVM's growing library of verification components can be used as a template. About OSVVM OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC. OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that: > Are simple to use and work like built-in language features. > Maximize reuse and reduce project schedule. > Improve readability and reviewability by the whole team including software and system engineers. > Facilitate debug with HTML based test suite and test case reporting. > Support continuous integration (CI/CD) with JUnit XML test suite reporting. >Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering. > Rival the verification capabilities of SystemVerilog + UVM. > OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses > > OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey. [1] https://blogs.sw.siemens.com/verificationhorizons/2020/12/16/part-6-the-2020-wilson-research-group-functional-verification-study/ Play webinar   

According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay rooted in one directory while it is advantageous to co-locate the user scripts with the verification IP they support. As a result, the scripts must manage the file source locations relative to the simulator directory. Further complicating the scripts is that each simulator API has a different way of specifying commands and command options. No wonder it is frustrating and messy. With OSVVM scripting, it is ok to hate TCL as it is unlikely you will use it directly. OSVVM creates a procedure-based API on top of TCL. User scripts are based on the OSVVM simple simulator command API that uses paths that are relative to the script's location. The messy TCL stuff is handled internally by the OSVVM command API. The result is that scripts include just a little more than a source file list. Generally, the most TCL that user scripts need is a simple if statement – but even this is rare (and there are examples in the OSVVM library). Not meaning to name drop, but OSVVM scripting supports Aldec's Active-HDL and Riviera-PRO, Siemens' ModelSim and QuestaSim, GHDL, Synopsys' VCS, and Cadence's Xcelium. With respect to reports, when we run a set of tests, we need to be able to assess whether all test cases passed or quickly identify which test cases failed. Once we have determined which test case failed, we need to have detailed information for each test case in a separate report that helps reveal the source of the issue. OSVVM's test reporting capability adds another reason as to why OSVVM should be your VHDL Verification Methodology. Our test reporting includes: > An HTML Build Summary Report for human inspection that summarizes the completion status of each test case in a test suite > A JUnit XML Build Summary Report for use with continuous integration (CI/CD) tools. > A separate HTML Test Case Detailed report for each test case with Alert, Functional Coverage, and Scoreboard reports. > An HTML based simulator transcript/log files (simulator output) > A text-based test case transcript file (from OSVVM's TranscriptOpen) > Links to tool generated code coverage reports Why do we go to all this trouble? When OSVVM runs its full regression suite, our build includes 22 test suites with a total of 524 test cases. The log file is 170K lines long. Without good tools we could not easily run our regressions and quickly assess whether it passed or failed. How well does OSVVM work with continuous integration tools? OSVVM uses our scripts and JUnit XML output when running our verification component regression suite on GitHub using GHDL. See https://github.com/OSVVM/OsvvmLibraries/actions. About OSVVM OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC. OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that: > Are simple to use and work like built-in language features. > Maximize reuse and reduce project schedule. > Improve readability and reviewability by the whole team including software and system engineers. > Facilitate debug with HTML based test suite and test case reporting. > Support continuous integration (CI/CD) with JUnit XML test suite reporting. > Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, > > > FIFOs, Memory Models, error logging and reporting, and message filtering. > Rival the verification capabilities of SystemVerilog + UVM. OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey.  Play webinar   

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional Coverage, Scoreboard, FIFO, and Memory data structures are now all based on singletons – in a similar fashion to what is done in AlertLogPkg. Using singletons significantly simplifies each data structure's USER API – the call interface. Specifically, users no longer need to use shared variables, protected types, and their complications. We will discuss the new APIs, their advantages, and some of the improvements OSVVM was able to make by using these. Don't worry though, we still support the older protected type data structures. One of the advantages of the updated data structures was discussed in Part 3 of this webinar series – reports for Functional Coverage and Scoreboards are automatically generated simply by running the tests with OSVVM scripting and calling "EndOfTestReports" rather than "ReportAlerts" at the end of the test. About OSVVM OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC. OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that: > Are simple to use and work like built-in language features. > Maximize reuse and reduce project schedule. > Improve readability and reviewability by the whole team including software and system engineers. > Facilitate debug with HTML based test suite and test case reporting. > Support continuous integration (CI/CD) with JUnit XML test suite reporting. > Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering. > Rival the verification capabilities of SystemVerilog + UVM. OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey.  Play webinar