Documentation Search in Resources Articles Manuals -OR- All Products Active-HDL Riviera-PRO ALINT-PRO HES-DVM HES Proto-AXI HES™ Boards RTAX/RTSX Adaptor Boards HES-DVM Proto Cloud Edition TySOM™ EDK Spec-TRACER DO-254/CTS All Documents Application Notes Manual Demonstration Videos FAQ Recorded Webinars Tutorials White Papers Technical Specification Case Studies All Categories Coverage 3rd Party Integration Design Entry, Documentation Simulation, Debugging Design Management, Libraries Advanced Verification Assertions and Functional Coverage RTL Simulation & Verification HDL Languages Encryption Military & Aerospace Verification Design Rule Checking Design Hardware Emulation Solutions Encryption Design HDL Languages RTL Simulation & Verification Assertions and Functional Coverage Advanced Verification Design Rule Checking Military & Aerospace Verification Hardware Emulation Solutions Tutorials Prototyping High-Level Synthesis Embedded Embedded Embedded High Performance Computer SoC & ASIC Prototyping Reset Results Name Products Type Action "Active-HDL not installed" message when running library installer Active-HDL FAQ "Browser.dat could not be opened" error during Active-HDL installation Active-HDL FAQ 01-Creating HDL Text Modules Learn how to create HDL Text Modules in Active-HDL Active-HDL Tutorials 02-Creating HDL Graphical Modules Learn how to create schematic diagram and finite state machine in Active-HDL Active-HDL Tutorials 03-Design Flow Manager Learn how to use Design Flow Manager in Active-HDL Active-HDL Tutorials 04-Creating Testbenches Learn how to create a Testbench in Active-HDL Active-HDL Tutorials 05-Running Simulation Learn how to run simulation and use waveform viewer in Active-HDL Active-HDL Tutorials 06-HDL_Debugging Learn how to use HDL debugging tools in Active-HDL Active-HDL Tutorials 07-Code_Coverage Learn how to use Code Coverage in Active-HDL Active-HDL Tutorials 08-Design_Profiler Learn how to use Design Profiler Active-HDL Tutorials 09-Documentation_Features Learn how to export designs to HTML and PDF in Active-HDL Active-HDL Tutorials 10-Simulink Interface Learn how to use Simulink® Interface in Active-HDL Active-HDL Tutorials ASDB Server Error Active-HDL FAQ Achieving RTL-to-Netlist Equivalence Simulation-to-Synthesis mismatch issues may cause malfunctions of physical devices. Even for functionally flawless RTL simulations, their physical implementation may contain critical design bugs. RTL Linting is the only way to locate and fix Simulation-to-Synthesis mismatch issues. The following article presents typical simulation-to-synthesis mismatch issues, illustrated by simple examples. For each one of described issues, the Lint checks are identified and explained. Active-HDL, Riviera-PRO, ALINT-PRO White Papers Active-HDL Does not Start after System Clock Time Change Active-HDL FAQ Active-HDL HDL Editor shortcut assignment Active-HDL FAQ Active-HDL Interface to Simulink® Active-HDL Application Notes Active-HDL Lattice Edition Active-HDL FAQ Active-HDL License Error: Cannot read data from license server system Active-HDL FAQ Active-HDL Manual Active-HDL Manual ... 292 results (page 1/15)
