Active-HDL Interface to Simulink®


In recent years, programmable logic devices have become key components in implementing high performance digital signal processing (DSP) systems, especially in the areas of digital communications, networking, video, and imaging. However, DSP designers conversant with programming in C or assembly language are often unfamiliar with digital designs that use hardware description languages (HDLs) such as VHDL or Verilog. Although VHDL provides many high level abstractions and language constructs for simulation, its synthesizable subset is far too restrictive for system design. The MathWorks' MATLAB®/Simulink® simulation environment provides a powerful high level mathematical modeling environment for DSP systems that can be widely used for algorithm development and verification.

Active-HDL provides an interface to MATLAB® and Simulink® simulation environment, which allows co-simulation of functional blocks described by using mathematical formulas and behavioral models described by using hardware description languages. The interface delivered with the Active-HDL installation program allows you to select a module or entity that will be used as a black-box during the verification process performed within Simulink. It can be used in both VHDL and Verilog designs and interfaces to the MATLAB environment through the mlab_cosim.dll library ($ALDEC\Simulink). The Simulink Interface also provides users with the following benefits:

  • Intuitive interface that fills the gap between HDL simulation and high level mathematical modeling environment for DSP systems

  • Displaying simulation results in both the Simulink environment and the Active-HDL waveform window

  • Automatic value conversion between Active-HDL and Simulink

  • Advanced test benches employing complex mathematical formulas used to stimulate unit under test Integration with Xilinx System Generator

Elimination of the INOUT Port Declarations from the Top Level Interface

Simulink® currently does not support the concept of bidirectional (INOUT) ports on its’ blocks. For that reason if your top level component’s interface (either VHDL or Verilog) contains any inout ports you will have to convert them to unidirectional ports before proceeding with the co-simulation process. A portion of VHDL code example is shown below on how to do this.

Before rewrite:

entity FPC is
     port (
      VCO: in BIT;
       RF: in BIT;
       RESET: in BIT;
       PLL_LOCK: out BIT;
       DOWN: inout BIT;
       UP: inout BIT
end FPC;

architecture FPCPLL of FPC is
signal S1,R2,Rs : BIT;
signal NAND1, NAND6, NAND7, Q1, QB2: BIT;
	NAND1 <= not(VCO and DOWN);
	NAND6 <= not(RF and UP);
	NAND7 <= '0' when RESET = '1' else not(NAND1 and Q1 and QB2 and NAND6);
	DOWN  <= not(NAND1 and Q1 and NAND7);
	UP    <= not (NAND6 and QB2 and NAND7);
end architecture;

After rewrite:

entity FPC is
   port (
      VCO: in BIT;
       RF: in BIT;
       RESET: in BIT;
       PLL_LOCK: out BIT;
       DOWN: out BIT;
       UP: out BIT
end FPC;

architecture FPCPLL of FPC is
signal S1,R2,Rs,s_up,s_down : BIT;
signal NAND1, NAND6, NAND7, Q1, QB2: BIT;
	NAND1 <= not(VCO and s_down);
	NAND6 <= not(RF and s_up);
	NAND7 <= '0' when RESET = '1' else not(NAND1 and Q1 and QB2 and NAND6);
	s_down  <= not(NAND1 and Q1 and NAND7);
	s_up    <= not (NAND6 and QB2 and NAND7);
	DOWN <= s_down;
	UP   <= s_up;
end architecture;

Interface Specification

Active-HDL provides the interface for The MathWorks' simulation tools, including:


  • Simulink

The interface supports the following features:

  • Output Data Types: Boolean, Unsigned, Signed (2's comp)

  • Number of Bits: Integer values between 1 and 52

  • Binary Point: 0 to 51

  • Quantization: Truncate, Round

  • Overflow: Saturate, Wrap, Error

Simulink Interface Setup

In order to perform a first time interface setup in MATLAB, follow the configuration procedure described below:

  1. Start MATLAB.

  2. Change the Current Directory in the MATLAB window to the $aldec\simulink directory.

  3. Enter the setup command in the MATLAB Command Window and press Enter. The appearing warning dialog box prevents you from accidental removing previous versions of the Active-HDL Blockset installed in MATLAB. Press Yes to continue. The following message should be displayed in the Command Window:

Welcome to Active-HDL Blockset Setup.

Removing previous version of Active-HDL Blockset from path:


Installing Active-HDL Blockset...

Adding Active-HDL Blockset path:


Active-HDL Blockset has been installed successfully.

  1. Choose the Set Path option form the File menu

    In this window you have to set the search path to the <Active-HDL Installation>\Simulink folder that contains some of the necessary files for the co-simulation. Choose the Save option and close the Set Path window by pressing the Close button.

    Preparing to do the Co-simulation in Active-HDL

    To start the co-simulation process in MATLAB’s Simulink environment, first you need to generate the Simulink description file (.m) for the top level entity or module of your HDL model . Active-HDL can do this automatically. To do that follow these steps in Active-HDL:

  2. Open a workspace and set an active design that contains HDL unit(s) to be co-simulated.

  3. Compile your HDL files representing the model you are going to co-simulate in Simulink (in our case it is fpc.vhd)

  4. Expand a source file (e.g. fpc.vhd) that contains the top level design unit that will be used as a HDL black-box in Simulink. Right-click on this unit (e.g. fpc(fpcpl)) and select the Generate Block Description for Simulink option from the pop-up menu.

    This option is unavailable if the design library is empty.

  5. Press Save to complete the MATLAB M-File generation.

    You will see the following messages in the console:

    simulinkgenmod -f -o "C:\My_Designs\FPC_PLL\Simulink\fpc.m" fpc fpcpll

    # Generating block description file: 'C:\My_Designs\FPC_PLL\Simulink\fpc.m'...

    # Generation of block description file for "fpc (fpcpll)" completed successfully.

    NOTE: If you would like to simulate several HDL entities on the Simulink’s diagram you will have to generate Block Description, i.e. the .m file, for each of the entity/architecture pair. When you run the Co-Simulation for Simulink, make sure to specify the same path in the Output Directory field for every HDL component you will simulate in MATLAB Simulink.


    Running Co-simulation in Simulink

  7. In Matlabs’s main window set the current folder to the location where we have generated .m files in Active-HDL. In our case it is C:\My_Designs\FPC_PLL\Simulink.

  8. Choose the Simulink icon from MATLAB's main toolbar to open the Simulink Library Browser window. In the left pane of the Simulink Library Browser window, the ALDEC Active-HDL Blockset library is displayed.

    All the blocks displayed in the Simulink Library Browser window can be added to a Simulink Model window. Refer to the Simulink on-line documentation for more information on creating Simulink Models.

  9. Create a New Simulink model and right click in the model free space to bring up the model properties screen as shown.

  10. Select Configuration Parameters option and left-click the mouse. The screen shown should appear.

  11. Set the Solver to “discrete (no continuous states) and the Type to “Fixed-step”, and set the Fixed-step size to the sample time desired, i.e. 1us for the example above means 1,000,000 samples per second in simulation time. So a simulation run of 1 second will have a million samples. Ensure the rest of the boxes are unchecked as shown above, Periodic sample time constraint is set to “Unconstrained”, and Tasking mode for periodic sample times is set to “Auto”.

  12. Add Active-HDL CoSim block to the SIMULINK model and open up the block by left-clicking on it and observe the screen as shown.

  13. Set the HDL Simulator and Simulink reference period to the desired period, in this case 1us is chosen. Ensure the Use Sampling Compatibility Mode box is checked and all other boxes are unchecked. Set the HDL Simulation Resolution to match the Reference Period as shown above, otherwise time skew will occur. Leave the rest of the defaults unchanged, i.e. make no more changes for now. Click on “OK”.

  14. Both a HDL Black-Box (see above) and the Active-HDL CoSim block may require additional parameters to be specified before the design is co-simulated

  15. The final part of the MATLAB model is to add the Black Box(s) for each entity to be co-simulated with AHDL and SIMULINK. Add the Black Box Simulink block to the model as shown.

  16. Select the appropriate “entity.m” file (this example it is fpc) and click OK. The block box is added to your model with the entity name appearing in the center of the block.

  17. Double click on the box and familiarize yourself with the parameter default configurations, but do not make any changes to the default settings for now.

    If waveforms are desired in Active HDL simply click on the Waveform tab and select the desired waveforms via the ADD button as shown in the screen.

  18. It is important to set both the Input and Ouput Ports Period to “1” as shown below. Select the Input Ports tab and Select the Period cell for each signal name, making sure to change the value from “Inherited” to “1”.

  19. Select the Output Ports tab and Select the Period cell for each signal name, making sure to change the value from “Inherited” to “1” as shown below. Select “OK” to save changes and close the box.

  20. Build test bench around Black Box(s) to complete MATLAB SIMULINK model for co-simulation.

    Note: It is important to rebuild all S-Function blocks connected to the HDL Black box(s) in the MATLAB SIMULINK model, should anomalies or time skew begin occurring in AHDL during the co-simulation process. Before rebuilding the model exit AHDL so no occurrences of AHDL are running.

  21. The next step is to save your MATLAB SIMULINK model upon completion, and ensure that AHDL is not loaded. Note: SIMULINK Unit Delay block is needed for proper co-simulation between an S-Function output and a HDL Black-Box input as shown above. If an S-Function is used the timing needs to be set to match the model configuration as shown below, i.e. Sample mode is “Discrete” and the Sample time value is set to the sample time of the model.

  22. Now run the MATLAB SIMULINK simulation and AHDL will automatically be launched after clicking the “CONTINUE” button. Step through the pre-load questions of AHDL and then a client connection will be made and the simulation is run until completion.

  23. It is not necessary to restart AHDL each time a new simulation is performed, just simply make desired changes in the MATLAB SIMULINK model, save the model if desired, and then restart the MATLAB SIMULINK simulation.

Adding non-port signals to Active HDL Waveform Viewer from Simulink

If waveforms within the HDL Black Box(s) are desired in Active HDL, i.e. those that don't show as outputs or inputs to a given a Black Box, simply open the Active-HDL Co-Sim block and click on the Script commands tab. Insert the desired waveform(s) with braces "{}" as shown with the wave command.

It is easy to obtain the parameters that follow the wave command by simply dragging the signal name to the command console in Active-HDL after simulation initialization. The signal name will appear with the appropriate path which is then copied and pasted as a Script command in the Post-initialization commands cell of the Active-HDL Co-Sim block as previously shown.

# Simulation has been initialized

# Selected Top-Level: dpll_matlab (cosimulation)

# /\DPLL_MATLAB/HDL Black-Box\/Q1 --console output from dragging waveform to command console window

# wave {/\DPLL_MATLAB/HDL Black-Box\/Q1} --add wave command and surround in braces

# 1 signal(s) traced.

# wave

# wave -noreg -notation unsigned -bin -height 15 "/DPLL_MATLAB/\DPLL_MATLAB/HDL Black-Box\/VCO"

# 1 signal(s) traced.

# wave -noreg -notation unsigned -bin -height 15 "/DPLL_MATLAB/\DPLL_MATLAB/HDL Black-Box\/RF"

# 1 signal(s) traced.

# wave -noreg -notation unsigned -bin -height 15 "/DPLL_MATLAB/\DPLL_MATLAB/HDL Black-Box\/RESET"

# 1 signal(s) traced.

# wave -noreg -notation unsigned -bin -height 15 "/DPLL_MATLAB/\DPLL_MATLAB/HDL Black-Box\/PLL_LOCK"

# 1 signal(s) traced.

# wave -noreg -notation unsigned -bin -height 15 "/DPLL_MATLAB/\DPLL_MATLAB/HDL Black-Box\/DOWN"

# 1 signal(s) traced.

# wave -noreg -notation unsigned -bin -height 15 "/DPLL_MATLAB/\DPLL_MATLAB/HDL Black-Box\/UP"

# 1 signal(s) traced.

# run -all


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