Documentation Search in Resources Articles Manuals -OR- All Products Active-HDL Riviera-PRO ALINT-PRO HES-DVM HES Proto-AXI HES™ Boards RTAX/RTSX Adaptor Boards HES-DVM Proto Cloud Edition TySOM™ EDK DO-254/CTS All Documents Application Notes Manual Tutorial Videos FAQ Recorded Webinars Tutorials White Papers Technical Specification Case Studies All Categories Coverage 3rd Party Integration Design Entry, Documentation Simulation, Debugging Design Management, Libraries Advanced Verification Assertions and Functional Coverage RTL Simulation & Verification HDL Languages Encryption Military & Aerospace Verification Design Rule Checking Design Hardware Emulation Solutions Encryption Design HDL Languages RTL Simulation & Verification Assertions and Functional Coverage Advanced Verification Design Rule Checking Military & Aerospace Verification Hardware Emulation Solutions Tutorials Prototyping High-Level Synthesis Embedded Embedded Embedded High Performance Computer SoC & ASIC Prototyping Reset Results Name Products Type Action Using ALINT with Aldec and Third-Party Simulators ALINT Application Notes Using Advanced Dataflow Active-HDL Application Notes Using Agilent SystemVue® Co-Simulation Interface Riviera-PRO Application Notes Using CVS Source Revision Control with Active-HDL Active-HDL Application Notes Using Components from Any Design’s Library by making the Library Global Active-HDL Application Notes Using Docker with Riviera-PRO Riviera-PRO Application Notes Using FPGA Based Simulation Acceleration in Typical ASIC Design Flow Abstract: Typical ASIC front-end and back-end implementation process involves HDL simulation as a method of verifying design netlist functionality at each stage of the flow. Although HDL simulation is considered accurate it suffers from very low execution speed.Aldec provides the DVM software that allows reusing your existing FPGA prototyping board as a platform for hardware acceleration of HDL simulation. HES-DVM, HES™ Boards White Papers Using FPGA Prototyping Board as an SoC Verification and Integration Platform Abstract: Size of new designs has grown so much that it easily allows creation of the entire system containing microprocessor unit and peripherals on one chip. Verification of such designs can no longer rely on software only, since simulation of MPU does not allow fast enough testing of application software and formal tools handle system hardware only. The use of FPGA-based prototyping boards creates fast and economical solution to this problem. This paper presents one practical implementation of Prototyping Board Verification and Integration Platform. HES-DVM, HES™ Boards White Papers Using NC-Verilog® Verilog-XL® scripts in Riviera-PRO Riviera-PRO Application Notes Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and others. This document presents Plot, a new solution for a graph-based analysis of HDL objects, correlations between them, and a number of practical applications for it. Riviera-PRO White Papers Using Riviera-PRO in Batch mode using Jenkins Software for Linux Riviera-PRO Application Notes Using Stimulators with the Accelerated Waveform Viewer in Active-HDL Active-HDL Application Notes Using Team Foundation Server with Active-HDL Active-HDL Application Notes Using Toggle Coverage Active-HDL Application Notes Using Waivers to Skip Irrelevant Violations ALINT-PRO Application Notes Using virtualization to save and restore a simulation Active-HDL, Riviera-PRO Application Notes VHDL Compilation Standards Active-HDL FAQ VHDL Performance Optimization Learn how to achieve ultimate VHDL simulation performance in Riviera-PRO Riviera-PRO Tutorials VHPI Applications Active-HDL, Riviera-PRO Application Notes VHPI Programing Active-HDL FAQ ... 623 results (page 27/32)
