VHDL Compilation Standards


I run into following compilation errors:

# Error: COMP96_0104: filename.vhd: Undefined type of expression.

# Error: COMP96_0077: filename.vhd: Assignment target incompatible with right side. Expected type 'STD_ULOGIC_VECTOR'>.

If we run compilation using acom -2008 or -2006 option COMP96_0071, COMP96_0104 and COMP96_0077 errors are detected. Meanwhile if we use acom -2002 option no warning is detected. Is it correct behavior based on VHDL 2008 standard?


There are some changes between version 2002 and 2008 regarding STD_LOGIC_VECTOR type declaration and STD_LOGIC_UNSIGNED package. Most of STD_LOGIC_UNSIGNED package has been moved to the NUMERIC_STD_UNSIGNED one.

Please simply comment previous and add NUMERIC_STD_UNSIGNED in the code:


For more information about migration please refer to VHDL 2008 Migration Tips chapter/section in our Help.

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.