SVUnit Adds Support for Aldec Riviera-PRO Users

A Guest Blog by Neil Johnson, HW Engineer/ Co-Moderator

Neil Johnson , HW Engineer/ Co-Moderator
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As I wrote on recently, Aldec users have something to get excited about as SVUnit now supports Riviera-PRO™, Aldec’s advanced verification platform. SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. It's automated, lightweight and easy to use for both design and verification engineers giving developers from either discipline the opportunity to prevent bugs in highly productive unit tests. ASIC and FPGA developers can use SVUnit to unit test code implemented in any SystemVerilog module, interface or class. Unit tests are automatically aggregated and run sequentially within a single executable thereby minimizing time lost to compilation and loading resulting in very fast run times and concise reporting.


Testing the Testbench

Poor testbench quality is an issue our industry has ignored for too long. Remembering that the testbench is the standard against which a design is measured, buggy testbench code means an unacceptable standard.


Verification engineers can use SVUnit to verify testbench components in isolation prior to being used in subsystem or chip/product level testbenches. Because SVUnit imposes very few restrictions on developers, it can be used to develop components for simple Verilog-based testbenches used for directed testing, complex SystemVerilog-based constrained-random testbenches and everything in between. SVUnit also supports development of UVM-based verification testbenches and IP.


Design Smoke Testing

Both verification engineers and the EDA industry as a whole have failed to provide a designer-friendly option for testing RTL prior to delivery to the verification team. The industry focus on constrained-random testbenches, OO verification constructs and complex methodologies has forced design engineers into building their own ad-hoc test fixtures for simple smoke testing. And while smoke testing can be a valuable checkpoint between designer and verifier, the overhead required to maintain the tests usually means smoke testing goes no further than a minimal subset of the code. Bugs are allowed to creep into the code base leading to time-consuming debug cycles.


With SVUnit, design engineers finally have an easy to use framework that lets them go further than merely smoke testing their design. SVUnit gives design engineers the option of taking responsibility for the quality of their code by unit testing critical logic or modules prior to release to the verification team; all while avoiding a lot of the overhead required to maintain an ad-hoc testbench. The result is higher quality code and an overall decrease in time lost to debug.


Focus on Quality with SVUnit

Bugs are not inevitable; neither are complex test methodologies. SVUnit is a simple alternative for both design and verification engineers that take pride in delivering high quality, bug-free code. SVUnit has a user base that's been growing steadily for 2 years and supports a number of industry leading simulators including Aldec Riviera-PRO. The SVUnit framework is available for download at


You can find examples, articles and information on writing high quality SystemVerilog code with SVUnit on

Neil Johnson has been working as a hardware engineer for over 15 years. He is a hardware test specialist and currently holds the position of Principal Consultant at XtremeEDA Corp, a design services firm specializing in all aspects of ASIC and FPGA development. He is co-moderator for, a site dedicated to the introduction of Agile development methods to the world of hardware development, as well as creative consultant to, a fictional EDA company run by 3 cartoon stick figures.

  • Products:
  • Riviera-PRO
  • Advanced Verification


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