Spec-TRACER offers traceability from FPGA/ASIC requirements to HDL design code and from verification test scenarios to a testbench code. This application note provides helpful tips when tracing from FPGA requirements to an HDL design and from test scenarios to testbench and test results.
Spec-TRACER has a direct interface to Active-HDL in order to facilitate traceability tagging operations. A connection between the active Active-HDL design and Spec-TRACER repository (DSN) and project must first be established before any tagging operations can be done. Upon connection, the Spec-TRACER repository and project information such as hierarchy, blocks, motives and requirements code, name and description are automatically read by Active-HDL.
To enable Spec-TRACER in Active-HDL, go to Design | Settings. Select the category Spec-TRACER and check the Enable Spec-TRACER checkbox.
Active-HDL GUI Design Settings: Enable Spec-TRACER
Select the category Spec-TRACER | Connection. In this window, users can select the specific Spec-TRACER repository and Project users would like to work on in Active-HDL. Enter the user credentials, and select the appropriate project in the Project field. Click Test Connection to ensure that connection to repository and Project is OK.
Active-HDL GUI Design Settings: Establish Connection
In the category Spec-TRACER | Project, users can configure how HDL and testbench tags in Active-HDL will be stored in Spec-TRACER. The Blocks field lists all of the available blocks within the design. Users will need to select the block in which the FPGA Requirements are stored. This will be displayed in the Requirements field.
NOTE: If users named the FPGA block by a different name, be sure to select to appropriate block.
Users will also need to select the block in which the Test Scenarios are stored. This will displayed in the Test Scenarios field.
NOTE: If users named the Test Scenarios block by a different name, be sure to select to appropriate block.
In the Store Settings area, users will need to select the block and motives where the HDL and Testbench tags will be stored. The Tags Construction Rules area contains the Prefix, Counter, and Postfix fields. The Prefix is what the user would like the tags to start with i.e. HDL_ and TB_. The Counter field is where the user can specify where the counting of the tags will start, i.e. 000. The Postfix is an optional field. The information as shown below is read by Active-HDL from Spec-TRACER.
Active-HDL GUI Design Settings: Spec-TRACER Project Settings
In the category Spec-TRACER | Results, users can configure how test results in Active-HDL will be stored in Spec-TRACER. The information as shown below is read by Active-HDL from Spec-TRACER.
Active-HDL GUI Design Settings: Spec-TRACER Results Settings
Once the user has applied the appropriate settings, the Spec-TRACER toolbar will be available.
View Spec-TRACER Window: This icon will open the Spec-TRACER window. This window is dockable within the Active-HDL environment.
Refresh Spec-TRACER Tree: This icon will refresh the contents within the Spec-TRACER tree.
Scan HDL Files: This icon will scan the HDL files for any existing, missing, or non-existent tags.
Capture Simulation Results: This icon will take the simulation log file that was created and export the information to Spec-TRACER.
In the Active-HDL environment, clicking on the Spec-TRACER () icon from the Spec-TRACER toolbar will display all of the FPGA requirements that are read from the Spec-TRACER repository and project. It contains complete information of requirements code, name, and description. Requirements that are marked with an () indicate that they have not been linked to any tags.
NOTE: The Spec-TRACER window is dockable and can be placed anywhere within the Active-HDL main GUI.
Active-HDL GUI: Design Browser Spec-TRACER Tab
To insert a tag in the HDL code, simply drag-and-drop the requirement element to a specific line of the HDL code. The HDL tag is created automatically and inserted into the code as a comment.
Active-HDL GUI: HDL Tag
The Spec-TRACER window displays a check () status showing that the requirement has been linked to an HDL tag.
Active-HDL GUI Design Browser Spec-TRACER Tab: Link Status
Users can also link tags to requirements in HDL designs file that contain existing HDL tags. To link the existing tags to requirements, highlight the HDL tag i.e. HDL_001 in the HDL file, right-click on the desired FPGA requirement code, and select Link tag. Make sure to exclude the comment symbols when highlighting.
Active-HDL GUI: Linking Tags Within Code
Active-HDL GUI: Link Tags
To verify which tags are linked to specific requirements, simply double-click on the requirement code in the Spec-TRACER window and the HDL Editor window will mark the code with an “x”.
Active-HDL GUI: Linked Tags Verification
Users can also print the tags to the console by right-clicking the requirement and selecting Print related tags.
Active-HDL GUI: Print Related Tags
Active-HDL GUI: Tags Printed to the Console
Double-clicking on the tags in the console will also bring the user to the relevant line within the HDL code.
Users utilize the Scan HDL files function to search the active HDL file for any existing tags. This is useful for tags that have been previously used in an HDL design.
Users can also link and unlink tags using the HDL Scan window. Clicking the Scan HDL files () icon will open the Scan HDL Files window. Clicking Search displays all existing tags along with the line number and status. The status types are:
Linked – the tag is linked to one or more requirements, and exists in the database
Unlinked – the tag is not linked to any requirement, but it exists in the database
Missing – the tag is linked to one or more requirements, but it is missing in the HDL file.
Non-existent – the tag is present in the HDL file, but is missing in the database
Active-HDL GUI: Scan HDL Files Option
Along with the Status of the tags, users can observe the Action that can be taken for those tags. If users check the box next to the action, when Apply is clicked, the action will be performed. For example, the action Remove will delete an existing tag. The Add option will add the tag to the database, but it will not be linked to an FPGA requirement.
NOTE: To remove an existing tag, delete it from the HDL code and then use the Scan HDL Files window to remove it from the database.
After the test scenarios are implemented in Spec-TRACER, users can establish tags from the test scenarios to an HDL testbench in Active-HDL.
NOTE: Users need to make sure to have a proper connection from Active-HDL to the Spec-TRACER REPOSITORY and project.
Select the Test Scenarios block (or whatever the user has named the Test Scenarios block) in Spec-TRACER tab. This will display all of the test scenarios.
Active-HDL GUI: Select Test Scenarios
Active-HDL GUI: Test Scenarios Displayed
To insert a tag in the testbench code, simply drag-and-drop the test scenario element to the specific line of the code. The TB tag is created automatically and inserted into the code as a comment.
Active-HDL GUI: Create Tags
The Spec-TRACER window displays a check () status showing that the test scenario been linked.
Active-HDL GUI: Test Scenario Status
Users can link existing tags, as well as use the Scan HDL Files window for removing linked tags. For more information, see the Viewing FPGA Requirements in the Spec-TRACER Window section of this document.
Simulations can be executed in the Active-HDL environment or a 3rd-party simulator. This application note assumes a simulation is performed within the Active-HDL environment. For more information about 3rd-party simulations, visit the resources page of the Aldec website.
Within the Active-HDL environment, users will need to compile all of the files within the design. Users can compile all of the files by right-clicking on the design in the Design Browser and selecting Compile All.
Compiling Design Files
After the design files are compiled, a top-level module needs to be selected. Users can expand the working library in the Design Browser, right-click on the testbench, and select Set as Top-Level.
Selecting the Testbench
Users will need to initialize the simulation before it can run. Select Initialize Simulation from the Simulation menu.
Initializing the Simulation
Once the simulation is initialized, users can add the testbench module to the waveform to view the simulation results. This is needed in order for users to trace the test scenarios within the waveform. To add the module to the waveform, right-click the testbench and select Add to Waveform.
Adding the Testbench to the Waveform
Once the testbench is added to the waveform, the simulation can be run. Users can use the Run, Run For, or Run Until options from the Simulation menu. Once a simulation has been performed, users can traverse the waveform using the test scenarios. This is especially useful for users who utilize hundreds of test scenarios and do not want to scroll through an entire waveform manually. Users can right-click on a specific test scenario and select Find in Waveform, and the waveform cursor will automatically move to that test scenario.
NOTE: The waveform window needs to be the active window in the Active-HDL environment in order for the option to be visible.
Test Scenario Find in Waveform Option
Waveform Cursor Moved to Specific Test Scenario
When users run a functional simulation in Active-HDL, the simulation results, which are saved in a log file, can be sent to Spec-TRACER. For more information on functional simulations in Active-HDL, see the Active-HDL User Manual.
When the simulation has completed, clicking on the Capture simulation results () icon will open the Simulation Results Exporting window. Clicking Add File allows users to input the simulation log file. The Search button will display the status of each test scenario.
Active-HDL GUI: Capture Simulation Results
Click Apply to send the results to Spec-TRACER. In Spec-TRACER each test scenario and its status will be displayed in the Items Grid Panel.
Client GUI: Grid Panel