Collecting Code Coverage in Active-HDL


Code Coverage is a technique that allows engineers to collect the statistics on the execution of each line of HDL code, and evaluate the quality of their tests. It is a relative measure of quality of verification.

Code Coverage can be roughly divided into statement coverage and branch coverage. Statement coverage provides information on which statements inside the VHDL or Verilog code were executed (covered) during simulation and how many times. Branch Coverage examines the execution of conditional statements (e.g. if statement, case statement). It provides the data on which branches were executed during the simulation, how many times each branch was executed, and how many times the branch condition evaluated to true or false.

Steps for collecting Code Coverage in Active-HDL

In this application note, we will use the freq_meter sample design that is shipped with the Active-HDL software.

  1. Open Active-HDL, go to File | Open Workspace/Design Explorer. In the Workspace/Design Explorer window go to Samples | VHDL_Designs and load the design named freq_meter.

  2. Enable the debug option to collect code coverage data. Go to the Design menu and select Settings… | Compilation | VHDL or Verilog and check the Enable Debug option.

    Figure 1. Enable Debug option in Design Settings

  3. To enable the code coverage option go to the Design menu and select Settings… | Coverage/Profiler and check the Coverage radio button. Select Code under coverage, you can also select other coverage types depending upon your requirements.

  4. Now, you can set the options for Code Coverage in Design | Settings… | Code Coverage as shown in the figure below.

    In the Output directory field, you will see the path to the folder where the file with results (results.ccl) will be created. If required, you can specify another location by pressing the browsing button (...). During the simulation, the simulator will write the Code Coverage data to this folder.

    When the Collect data per instance checkbox is selected, the coverage data will be collected separately for each instantiated object. The Code Coverage Viewer displays this information in a separate tab - Instances. By default, this option is not set, and Code Coverage collects the data on a per-unit basis.

    The Collect data for all units checkbox determines whether the coverage data should be limited to objects residing in the current working library or extended to objects from external system libraries as well.

  5. Compile all files in the design by selecting Design | Compile All from the main menu. Once the design is compiled successfully, set the top-level as shown in the picture below.

    Figure 4. Setting Testbench as top-level

  6. Now, initialize the simulation. Select Simulation | Initialize Simulation from the main menu. Run the simulation for 25us. Code Coverage data is gathered during the simulation, however, the file specified in the Output directory field is created when the simulation is stopped. Stop the simulation by selecting Simulation | End Simulation from the main menu.

  7. Invoke the Code Coverage Viewer. Select Tools | Code Coverage Viewer from the main menu. In the Code Coverage Viewer window, choose Open (Ctrl+O) from the File menu and point to the file containing the Code Coverage data (i.e. results.ccl). Double-click the results.ccl file or select it and press Open. The Code Coverage data is loaded into the Code Coverage Viewer window as it is presented in figure below.

    Figure 5 The Code Coverage Viewer window

    The Source Code window has the following columns:

    • Line

      Displays the line numbers of the source code.

    • Count

      Shows how many times each line of the HDL code was executed. If a line contains more than one executable statement, the count number is followed by an asterisk. Moving the mouse pointer over that line displays a tooltip with execution counts for each statement.

    • BC

      Displays Branch Coverage data for the IF or CASE constructs. When the source code contains the IF construct, the BC column displays the number of conditions that evaluated to True (e.g. 4t) and the number of conditions that evaluated to False (e.g. 2f) during the simulation. True (t) means that the condition in the selected if branch was met and this branch was executed. False (f) means that the condition in the if branch was not met and the elsif or else branches were executed instead. The total number of executions is displayed in the Count column. When the source code contains the CASE construct, then the BC column displays the number of when branches that were covered (executed) and the total number of branches within the construct.

  8. By selecting the Details tab in the right pane, you can see Code Coverage summary in the form of graphical charts.

    Figure 6 The Details tab of the Code Coverage Viewer window

    The upper part presents the results generated by the Code Coverage engine. The results for the selected item chart shows the number of executed statements for the selected instance in green, and the number of statements that were not executed within this instance in red.

    The lower part presents the results generated by the Branch Coverage engine. The Branch Coverage for the selected item chart shows the number of executed branches for the selected instance in green and the number of branches that were not executed in red.

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