Why Randomize?

Guest Blog with Jim Lewis, VHDL Training Expert at SynthWorks

Jim Lewis, VHDL Training Expert at SynthWorks
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After presenting a conference paper on how to do OSVVM-style constrained random and intelligent coverage (randomization based on functional coverage holes), I received  a great question, "Why Randomize?"

The easiest way to answer this is with an example.  Let's look at a FIFO test - test a FIFO, write to it, read from it, write to it and read from it simultaneously, fill it and see that additional writes are held off successfully, and empty it and see that additional reads are held off successfully. 

Most certainly a FIFO can be tested using a directed test (just code, no randomization).  The following simulation waveform shows diffcount (the number of words in the FIFO) for a directed test.   The lowest value is empty.  The highest is full.  Using this, you can visually check off all of the required conditions and see that the FIFO is indeed tested.


We can also test a FIFO using randomization.  In this approach, we try to emulate the interface behavior of the FIFO.  The FIFO write interface receives bursts of writes and then is idle for some period of time.   The FIFO read interface works the same way.  The following waveform also shows Diffcount.  Looking at the waveform, you can also see that this covers the required conditions.


Both the directed and the randomized test cover the required conditions.  However, the randomized test does a much better job generating realistic stimulus that covers different variations in the design space.  Hence, it is more likely to find bugs - particularly ones we do not anticipate.

Randomization is ideal for tests that have a large variety of similar items, such as different configurations/modes, processor instructions, and network packets.  Randomization can be much more thorough than other approaches since stimulus is not ordered.  Randomization can generate a large volume of realistic stimulus (hopping between different modes in a non-sequential fashion) in a timely fashion (to write).

Randomization is not for everything.  Hence, you will need a testbench environment that is flexible and allows mixing directed, algorithmic, file based, constrained random, and intelligent coverage techniques. 

To learn more about high-level synthesis and its benefits, view Recorded Webinar: VHDL Testbench Techniques that Leapfrog SystemVerilog.



Jim Lewis, the founder of SynthWorks, has twenty-eight years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis does ASIC and FPGA design, custom model development, and consulting. Mr Lewis is a founding member of the Open Source VHDL Verification Methodology (OSVVM) and the principal architect of its packages and methodology. Mr. Lewis, who holds a BSEE, BSCEE, and MSEE from Purdue University, serves as chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG).


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