Play Webinar

Title: VHDL Intelligent Coverage™ using Open Source - VHDL Verification Methodology (OS-VVM) with Guest Presenter, SynthWorks

Description: At the lowest level, Open Source - VHDL Verification Methodology (OS-VVM), is a set of packages that provide concise and powerful methods to implement functional coverage and randomization. OS-VVM uses these packages to create an intelligent testbench methodology that allows mixing of "Intelligent Coverage™" with directed, algorithmic, file based, or constrained random test approaches. Having an intelligent testbench approach built into the coverage modeling puts OS-VVM a step ahead of other verification methodologies, such as SystemVerilog and UVM. Attend this webinar and learn how to utilize OS-VVM to add functional coverage, Intelligent Coverage, and constrained random methods to your current testbench.

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