Camouflage for Your HDL Code

Mariusz Grabowski, FPGA Design and Verification Engineer
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Designers may deliberately obfuscate HDL code to conceal its purpose (security through obscurity) or its logic, in order to prevent tampering and deter reverse engineering. The obfuscated code is unreadable to the receiving user, but is still readable to compilers and simulators. This way obfuscation also comes in handy when you need to share your source code with an EDA tool vendor for debugging and don't want the recipient to see the contents of the actual file. Aldec provides the script to obfuscate VHDL, Verilog, and SystemVerilog code.

For steps to execute this script, see related App Note, HDL Code Obfuscation.

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).

  • Products:
  • Active-HDL
  • FPGAデザイン・シミュレーション,
  • Riviera-PRO
  • Advanced Verification

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