U.V.M. Spells Relief

Create robust test environments with ease

Henry Chan, Technical Support Engineer
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Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly.


So what is UVM?

UVM is a verification methodology based on an earlier verification methodology (OVM 2.1.1 developed by Cadence and Mentor Graphics). Accellera used this OVM base, continued development, and now maintains it as a more modern and updated version in UVM. Tangibly, UVM is a library of SystemVerilog code that is intended to help engineers write effective test and verification environments. You can download the UVM class library code, user guide, and reference documents from Accellera’s website.


Key Benefits of UVM:

1. Constrained Random Stimulus

The problem is: testing all possible combinations of a design’s signals will take too long to simulate. UVM addresses this by constraining the stimulus to certain values and randomizing specific cases for maximum coverage. The control you have over your test pattern generation is unprecedented. Generating customized sequences of signals that will push your design into desired corner cases is easy with UVM.

2. Code Reuse

UVM was designed to provide a ton of ‘boilerplate’ code that can be reused. There is no longer a need to start from scratch for each different design. Make efficient use of your time by copying and pasting a verification environment from a previous project and simply make small adjustments.

3. Standard Verification Methods

As UVM adoption proliferates, verifying your designs using a standard methodology provides consistency among the engineering community. Your verification environment will be understood by other engineers, including team members. Send your files to others without having to explain your verification methods. You will even be able to troubleshoot your verification environment by visiting forums dedicated to UVM for information.


How does UVM work?

The UVM Class Library provides all the tools necessary to begin creating an effective and reusable test environment. The image in figure 1 shows some of the classes and methods within the library.

Figure 1 – UVM Class Diagram

Honestly, it may seem intimidating at first because there are many different components, but once you become familiar with the structure of UVM and the specific roles of each component, things get easier quickly because it’s still the same verification flow that is typically used, except more organized and modularized.


Upgrading your verification using UVM

Typical Non-UVM verification flow involves:

1. Instantiating the design under test (DUT)

2. Generating and applying test stimulus to the DUT

3. Observing the output to determine if the design is producing the correct results.


UVM also does this, but more systematically and in a more compartmentalized way so that any verification code you write for one design may be reutilized for other designs. Let’s take a look at a very basic UVM testbench architecture and some of its components.

Figure 2 – Typical UVM Testbench Architecture

Typical verification flow/architecture using UVM:

1. Instantiate the design under test (DUT) and its interface(s)

a. An interface is simply a collection of signals/ports with a designated purpose, for example:

i. Control signals

ii. Data signals

iii. Communication signals

2. Instantiate the test class that will house the testing components

a. Sequences that describe test stimulus behavior

b. Environment with a configuration database – similar to passing parameters or generics in VHDL

i. Agents that house:

1. Sequencers – takes transactions from Sequences (from the Test class) and filter them to the Driver

2. Drivers – apply the Sequence transactions (test stimulus) to the DUT through the interface

3. Monitors – captures the output transactions from the DUT interface

ii. Use the Scoreboard to check the correctness of the design by obtaining values from the Monitor and compare them with expected values


Riviera-PRO UVM Features

Many mainstream simulators already provide features to accommodate your UVM endeavors, including Aldec’s Riviera-PRO.

Figure 3- Riviera-PRO UVM Graph

The Riviera-PRO UVM Graph allows users a better understanding of their verification environment by providing a graphical representation of the UVM hierarchy.


Related: Visualizing UVM Environments: Debug Features Deliver a Clearer View

Figure 4 – Riviera-PRO’s UVM Hierarchy and Configuration Windows

And if a graph isn’t your style, you can view the UVM hierarchy and configuration windows to get more information on your verification environment.


Late bloomers?

With all the benefits which UVM can provide, there is still contention with non-adopters stating that UVM is complicated and learning a new verification method will take too long.


Yes, learning UVM will take some time and effort, but in the long run it will be worth it. Designs in the EDA industry are growing at an incredible pace, and making sure those designs are bug-free is a monumental task. Adopting UVM sooner rather than later will ensure that you have the skills and knowledge to be able to verify increasingly complex designs and stay at pace with the industry. Aldec even offers a Fast Track to UVM Training course and webinars to help you learn more about UVM.


Have the confidence to tackle any design

UVM organizes the verification paradigm and provides a set of tools to facilitate effective verification. With the verification process becoming more optimized under UVM, you can feel more secure knowing that you will be able to successfully verify any design that comes your way. As the industry continues to adopt the standard, verification is only going to get easier, what are YOU waiting for?

Henry provides support to Aldec customers as a Technical Support Engineer. Specializing in Active-HDL™ and Riviera-PRO™, he is well versed in Aldec’s industry leading FPGA design and simulation tools as well as digital design and verification of FPGA solutions. Henry received his B.S. in Computer Engineering from the University of Nevada, Las Vegas in 2015. His in-depth knowledge of hardware description and verification languages makes him adept at solving complex FPGA problems.


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