‘Don’t Be Afraid of UVM’ Webinar on YouTube

Free webinar from the Aldec archives

Sunil Sahoo, Corporate Applications Engineer
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Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube.

Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design.

Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module.


To learn more about Aldec Solutions, please contact us at sales@aldec.com or call +1-702-990-4400.



One final note. Those not familiar with Object Oriented Programming (OOP) and Transaction-Level Modeling (TLM) are strongly encouraged to view our previously recorded webinars: "Know Your Objects - OOP for Hardware Designers" and "TLM Concepts for Hardware Designers".

Sunil provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions that include Digital Design Engineer Verification Engineer and  Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.

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