Helping FPGA Designers get started with UVM

Guest Blog by Doulos CTO, John Aynsley

John Aynsley, Doulos CTO
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UVM (the Universal Verification Methodology for SystemVerilog) represents best practice in constrained random functional verification, so it is something that every digital design and verification engineer should be aware of.

However, even if you already have a sound understanding of SystemVerilog, UVM is in itself complex and challenging to learn and use; a daunting prospect, particularly if you are an FPGA designer with limited time to dedicate to verification.


The challenge of getting your first UVM project off the ground


Even assuming the highest quality training, there is still a need for further help to get started with the first project. UVM can take some time to adopt – in some areas there is more than one approach to choose from, there are optional shortcuts and new features that may or may not work for you and finding good quality advice can be hard and time-consuming in the absence of a definitive methodology. Many have observed that UVM is still in need of a “methodology”, in the sense of a definitive set of rules and guidelines directing its use.


Making the path to UVM adoption Easier


Since the introduction of UVM in 2011, Doulos has been developing Easier™ UVM to act as a starting point for learning UVM and it has now evolved into a comprehensive set of coding guidelines with an open-source UVM code generation tool. This development has been made possible by the unique insight the Doulos team has gained through working with many different customers going through the experience of UVM adoption in multiple industry contexts.


The Easier UVM code generator creates project-specific boilerplate UVM code according to the Easier UVM guidelines. Together, these help individuals and teams to get started with UVM, avoiding pitfalls and following best practice, and help to ensure consistency and uniformity across projects. Easier UVM helps teams to accelerate UVM adoption, and reduces the burden of maintaining a UVM codebase over time. Both the guidelines and the tool can be taken as they are or can be used as a starting point and modified according to the demands of a specific project.


Want to find out more?

Make sure you check out this recorded webinar Easier UVM: Helping FPGA Designers Get Started with UVM.  Presented by Doulos CTO John Aynsley, this 1 hour webinar will help you uncover how Easier UVM can work for you. 


John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specializing in hardware description and verification languages, in particular VHDL, SystemC, SystemVerilog, and now UVM.

John served as technical lead and author of the IEEE Standard 1666-2011 SystemC Language Reference Manual, as well as implementing the 1666-compliance regression test suite for the Accellera Systems Initiative proof-of-concept SystemC simulator. In February 2012 John received the Accellera Systems Initiative Technical Excellence Award in recognition of his contribution to SystemC standardization.

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