U.V.M. Spells Relief

Create robust test environments with ease

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief.

Live Webinar: Getting into SystemVerilog from VHDL

Guidance from a VHDL Guru

In this December 18th webinar, Doulos Senior Member Technical Staff, Doug Perry (author of 'Programming By Example') will provide a VHDL Guru's perspective on SystemVerilog and UVM.

Push the UVM Start Button, then Hit the Accelerator

By Doug Amos, One-Man-Army FPGA Consultant

Maybe you’ve taken a good look and decided that the Universal Verification Methodology for SystemVerilog (UVM) is not for you. This article won’t help you learn it, but it will point you to how you might speed up your UVM learning, your UVM adoption and even your UVM execution throughput.

The Problem with CDCs

And how it affects your DO-254 project

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design.

Extend Vivado Capabilities with Help From the Tcl Store

Xilinx Vivado Tutorial: Upgrade for increased simulation performance

Outgrowing something can be hard. So hard, that sometimes we live in denial longer than we should. We are resistant to change, often because we are simply too comfortable with what we know (or too busy) to consider the options.

In The News

Aldec HES™ Co-emulation named a finalist in this year’s ARM® TechCon Innovation Challenge

Aldec Introduces Hybrid Emulation with ARM® Fast Model Support

50+ Successful DO-254 Projects Supported by Aldec’s FPGA Test System; Now with Pre-Tool Qualification Data Package