It's never too late to assertion verification Jan 21 (Webinar, Online) Best Practices for Mixed-Language FPGA Design and Verification (US) Jan 22 (Webinar, Online) Best Practices for Mixed-Language FPGA Design and Verification (EU) Jan 22 (Webinar, Online) Running CDC Analysis with Xilinx Parameterized Macros Jan 28 (Webinar, Online) FPGA HORIZONS Apr 29 - 30 (Industry Event, Worcester, MA) View all events
Boost FPGA Reliability with Advanced Linting and CDC Analysis Bridging Simulation and Hardware: Hardware-in-the-Loop in Action Advanced Static Linting Techniques for High Performance Design Optimization HDLRegression – Automated Regression Testing for VHDL/Verilog FPGA Verification with VHDL and UVVM Part 2: Harnessing the power of VVCs and BFMs View all webinars
ALINT-PRO™ Adds New Mixed-Language Design Rules for More Predictable Cross-Language Integration January 14 What’s involved in simulation of a complex SoC FPGA like Versal ACAP? February 08 Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs June 26 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs June 14 The avionics industry’s growing need for TLM May 18 View all news
