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100% Signal Visibility during Emulation Dynamic Debug with HVD Technology   
Abstract: When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization. Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code. Play webinar   
HES-DVM Recorded Webinars
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM White Papers
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Functional verification of a design at the three design stages (RTL, Gate-Level and Post-Route) are essential steps to ensure correct behavior of a design according to requirements, however they are limited by HDL simulator speed. While HDL simulators offer advanced debugging capabilities and provide robust design coverage information, their speed is the primary bottleneck of the design cycle when it comes to verification. This webinar will discuss a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Accelerating Simulation of Vivado Designs with HES    HES-DVM Application Notes
Accelerating The Verification Of Hardware Dependent Software   
Software costs now dominate in SoC design. It is therefore imperative that the dependencies the hardware places on the software are captured and managed as early as possible. To ignore these is to risk project and budget overrun. In this webinar, we will illustrate why FPGAs are chosen as the verification platform for software integration. We will discuss the challenges of using FPGAs for verification and introduce the use of hybrid virtual prototypes. A comparison will be made between traditional FPGA ASIC prototypes and an FPGA-based emulation system. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Accelerating UVM Verification with Emulation   
In this video, Application Engineer Henry Chan, explains how emulation can help accelerate UVM-based testbenches and explores the benefits of emulation/acceleration over traditional simulation tools. A cursory overview of the Accellera SCE-MI standard as well as some necessary testbench modifications for emulation/acceleration are presented. A case-study using a UVM testbench and Network-on-Chip design is examined to demonstrate the benefits of emulation.
Riviera-PRO, HES-DVM Demonstration Videos
Aiding ASIC Design Partitioning for multi-FPGA Prototyping   
Whether it is an ASIC, ASSP or large FPGA design, emulation and prototyping are indispensable verification and validation activities. Often FPGA based platforms are chosen due to their scalability and versatility and more importantly, because of their runtime speed potential. What drives many away from this platform are the challenges of the multi-FPGA design setup that requires complex partitioning, arranging interconnections and managing multiple clock domains across multiple devices. Automation in this field is highly desirable to avoid time consuming and error prone hand-crafting and design hacks that would enable FPGA prototyping. Aldec HES™ Prototyping Platform and related solutions are here to mitigate these risks and facilitate rapid implementation of reliable FPGA prototypes. Design setup for a large multi-FPGA platform is facilitated with the HES-DVM tool that provides new partitioning utilities and can convert ASIC clocks to FPGA-proof structures. Awareness of clock domains and prototyping board connectivity resources facilitates in making wise decisions and allows achieving high clock ratios of FPGA prototypes. In this webinar, we will demonstrate the new HES-DVM prototyping flow that will increase your productivity in physical prototyping by shortening the setup time and increasing runtime speed of your design in FPGA.  Play webinar   
HES-DVM Recorded Webinars
Can I put some of my many modules in Hardware and additional modules later without having to re-compile?    HES-DVM, HES-EDU FAQ
Debugging SCE-MI Co-Emulation in Riviera-PRO   
Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation.
Riviera-PRO, HES-DVM White Papers
Designing UVM Testbench for Simulation and Emulation of Network-on-Chip Design   
Universal Verification Methodology (UVM) is one of the most popular approaches in using transactional testbench environment. The growth of SoC designs forces design and verification teams to use emulation as a way to speed-up verification process. Standard CoEmulation Modeling Interface (SCE-MI) provides ways to connect emulated design with transactional testbench. This paper describes how to use SCE-MI to create UVM test environment that is ready for both simulation and emulation.
HES-DVM White Papers
Does HES-DVM include any tools for prototyping?    HES-DVM, HES-EDU FAQ
Does HES-DVM provide a scripting interface?    HES-DVM FAQ
Does HES-DVM support FPGA Hard-Marcros?    HES-DVM FAQ
Does HES-DVM support Xilinx ChipScope PRO Debugging Tool?    HES-DVM FAQ
FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond   
As today's SoC and ASIC designs evolve to integrate the latest embedded processors, media interfaces, and high-speed serial communication, FPGA prototyping platforms are struggling to maintain the pace of designs surpassing the 100 million ASIC gate count. With the evolution of modular architectures and robust scalable backplanes, FPGA prototyping vendor solutions such as Aldec HES-7™ are able to keep pace with hardware designers. The HES-7 backplane enables scaling up to 96M ASIC gates, which can be serially daisy-chained for designs which require additional capacity. Play webinar   
HES-DVM, HES-7 Recorded Webinars
FPGA Accelerator for Genome Aligner - ReneGENE   
Abstract:
Aldec industry partner, ReneLife introduces its proprietary core technology, ReneGENE, for fast and accurate alignment of short reads obtained from the Next Generation Sequencing (NGS) pipeline. The technology, devoid of heuristics can precisely align the DNA reads against a reference genome at a single nucleotide resolution. As genomics permeates the entire landscape of biology, including biomedicine and therapeutics, ReneGENE creates a genomic highway that significantly contributes to reduce the time from sample to information without compromising on accuracy, critical for lifesaving medicare applications, biotechnology product development and forensics.

In this webinar, we present AccuRA, a high-performance reconfigurable FPGA accelerator engine for ReneGENE, offered on Aldec HES-HPC™ for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the NGS platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on a 8-core 3.5 GHz AMD FX™ processor with a system memory of 16 GB. AccuRA employs a scalable and massively parallel computing and data pipeline, which achieves short read mapping in minimum deterministic time. It offers full alignment coverage of the genome (million to billion bases long), including repeat regions and multi-read alignments. AccuRA offers a need-based affordable solution, deployable both in the cloud and local platforms. AccuRA scales well on the Aldec platform, at multiple levels of design granularity.

Agenda:
  • Introducing the world of genomic big data computing
  • The need for accuracy and precision
  • Introducing ReneGENE/AccuRA
  • Product Demo
  • Impact of ReneGENE-The Genomic Highway
Presenter: Santhi Natarajan, Ph. D (IISc) Play webinar   
Riviera-PRO, HES-DVM, TySOM™ EDK Recorded Webinars
FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms   
Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically referred to as ASIC FPGA prototyping. At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of these systems. In this webinar we will introduce an approach where UVM tests can be accelerated with the use of an FPGA co-emulator. The approach is built upon industry standards SystemVerilog and SCE-MI, and requires no changes to the test environment to accelerate. This enables tests to be moved seamlessly from simulation to the accelerator and back again. Play webinar   
HES-DVM, HES-7 Recorded Webinars
HES™ Overview: A Hybrid Verification and Validation Platform   
Aldec Hardware Emulation Solutions is a hybrid verification and validation ecosystem for hardware and software teams developing the latest SoC and ASIC designs. Partnering the latest high-capacity FPGA technology with industry leading co-emulation standards, HES allows for multiple modes of verification and validation including bit-level simulation acceleration, transaction-level emulation, Hardware prototyping, and Virtual Modeling.
HES-DVM Demonstration Videos
How do I change the Verilog timescale for the HES-DVM generated wrapper file?    HES-DVM, HES-EDU FAQ
How do I download the bit files compiles from HES-DVM in HES-proto mode?    HES-DVM FAQ
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