Name Products Type Action
Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting   
Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.  This second webinar of a two-part “Fast Track” series is designed to help functional verification engineers get up to speed quickly. In this webinar, you’ll learn about more debugging tips and we’ll also cover Tracing Logic and how to run code coverage in Riviera-PRO. We’ll also take a look at Plots - a new way of analyzing results.  Play webinar   
Riviera-PRO Recorded Webinars
#ELBREAD: Warning: Module 'module_name' does not have a `timescale directive, but previous modules do.    Riviera-PRO FAQ
1.0 Riviera-PRO™ Overview: Advanced Verification Platform   
Riviera-PRO™ addresses verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
Riviera-PRO Demonstration Videos
2.1 Design Entry: Design Manager & Perspectives   
Managing your design and workspace effectively in Riviera-PRO. Running simulations without creating a design and a workspace.
Riviera-PRO Demonstration Videos
4.1 Debugging: Bookmarks, Delta Cycle and Virtual Grouping in Waveform Viewer   
Advanced waveform operations using bookmarks with comments, opening delta cycle to debug race conditions and virtual grouping and virtual arrays for searching through combination of signals, bits.
Riviera-PRO Demonstration Videos
4.10 Debugging: Splitter, Signal Breakpoint and Cross Probing    Riviera-PRO Demonstration Videos
4.2 Debugging: Browsing, Finding and Measuring in Waveform Viewer   
Basic Waveform operations like browsing using advance modes, finding objects and values, utilizing multiple cursors and sub cursors for time and frequency measuring.
Riviera-PRO Demonstration Videos
4.3 Debugging: Comparing Datasets   
Comparing two different simulation datasets for differences in signals values.
Riviera-PRO Demonstration Videos
4.4 Debugging: Datasets, Hierarchy Viewer and Object Viewer   
Managing your simulation datasets, exploring your design hierarchy and design objects. Loading multiple simulation datasets for debugging and comparison.
Riviera-PRO Demonstration Videos
4.5 Debugging: Drivers/Readers and Advance Dataflow   
Tracing the signals to their drivers and readers from the level of your HDL code.
Riviera-PRO Demonstration Videos
4.6 Debugging: Plots - A Powerful Alternative to Waveforms   
The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and others. This video presents several practical applications for Plot, a new solution for a graph-based analysis of HDL objects and correlations between them. The presentation is followed by a quick hand-on demo of the actual tool.
Riviera-PRO Demonstration Videos
4.7 Debugging: Saving Waveform Configuration and Snapshot   
Saving waveform configuration to a macro file for reuse, creating a copy of a simulation datasets using 'Save waveform snapshot' option.
Riviera-PRO Demonstration Videos
4.8 Debugging: UVM Transactions Debugging   
UVM Transactions Debugging
Riviera-PRO Demonstration Videos
4.9 Debugging: Xtrace and Advance Dataflow   
Visualizing the hierarchy and the connectivity of an active design and analyzing the dataflow among the instances, concurrent statements, nets and registers. Monitoring the design for undesired and unknown values using Xtrace. Combining Xtrace with Advanced dataflow for quick exploration of the drivers of unknown values.
Riviera-PRO Demonstration Videos
Accelerate DSP Design Development: Tailored Flows   
Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Accelerating UVM Verification with Emulation   
In this video, Application Engineer Henry Chan, explains how emulation can help accelerate UVM-based testbenches and explores the benefits of emulation/acceleration over traditional simulation tools. A cursory overview of the Accellera SCE-MI standard as well as some necessary testbench modifications for emulation/acceleration are presented. A case-study using a UVM testbench and Network-on-Chip design is examined to demonstrate the benefits of emulation.
Riviera-PRO, HES-DVM Demonstration Videos
Achieving RTL-to-Netlist Equivalence   
Simulation-to-Synthesis mismatch issues may cause malfunctions of physical devices. Even for functionally flawless RTL simulations, their physical implementation may contain critical design bugs. RTL Linting is the only way to locate and fix Simulation-to-Synthesis mismatch issues. The following article presents typical simulation-to-synthesis mismatch issues, illustrated by simple examples. For each one of described issues, the Lint checks are identified and explained.
Active-HDL, Riviera-PRO, ALINT-PRO White Papers
ACOM: Error: COMP96_0153: Formal "name" of class variable must be associated with a variable    Riviera-PRO FAQ
ACOM: Error: ELAB1_0021: filename.vhd: Types do not match for port "port_name"    Riviera-PRO FAQ
Addressing the Challenges of SoC Verification in practice using Co-Simulation   
Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing systems (PS) with state of the art programmable logic (PL). This combination allows system to be architected to provide an optimal solution. Verifying this interaction between the PS and PL presents a challenge to the design team. While each can be verified in isolation using QEMU for the PS and Riviera-PRO for the PL. The integration between the PS and PL all too often takes place late in the design cycle when the impact of addressing issues raised is larger in both time and cost. There is however, another way which is Co-Simulation, which can be performed early in the development cycle. This webinar will explore the challenges which are faced by SoC users, introduce the concept of Co-Simulation and its constituent parts along with demonstrating advanced debugging techniques. We will examine the required environment and pre-requisites needed to perform Co-Simulation. Detailed examples will then be presented to demonstrate basic and advanced debugging concepts. Based upon a Zynq implementing a Pulse Width Modulation IP core operating under SW control. We will look at examples which introduce basic Co-Simulation flow like waveform inspection along with advanced debugging aspects such as software and Hardware breakpoints and single stepping. These techniques will enable us to identify and debug issues which reside in both the software and hardware design. Co-Simulation enables you to develop your application faster and reduce the bring up time once the application hardware arrives for integration. This webinar will demonstrate these benefits and more which are gained when Co-Simulation is used, while demonstrating the ease with which the environment can be established and simulation performed. Play webinar   
Riviera-PRO, TySOM Boards Recorded Webinars
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