Resources

In this webinar, Chris Higgs of Potential Ventures will demonstrate what is arguably the most productive RTL development flow in the world. By tightly coupling the hardware and software elements into an engineered flow, a rapid and agile approach to FPGA development becomes possible. Taking the best of open and closed source tools, Potential Ventures have created a flow that stands up to the rigorous demands of the cutting edge financial services sector where project times are measured in days and weeks rather than months and years. The webinar will cover all aspects of RTL development including verification, regressions, co-simulation of hardware and software, interactive debug tools, documentation, metric tracking and more. Play webinar   

Learn how to debug your code in Riviera-PRO

Mission-critical FPGA designs for space and radar applications continue to increase in complexity, such that they require a comprehensive and robust verification environment. There are hardware-in-the-loop solutions in the market that utilize FPGA boards, but when it comes to establishing functional coverage and debugging the custom logic, users would typically need to go back to HDL simulation. As a result, HDL simulations are becoming excessive and they have become the primary bottleneck when it comes to verification. In this paper we will describe a solution that can accelerate HDL simulation for the system FPGA design that includes the custom logic and reused IP Cores where the testbench executes in the simulator and the synthesizable parts of the design is implemented in a Microchip FPGA board.

Abstract: This paper presents a new approach in domain of high level digital circuits simulation and modeling that benefits from high level mathematical environment delivered by MATLAB. It allows to integrate design process and directly verify obtained results with mathematical formulas or complex operations that are not available in standard HDL languages. A part of HDL code can be placed for verification purposes inside the advanced mathematical model or can execute complex calculation. Paper presents problems that are introduced by hybrid simulation and modeling environment concerning data representation, simulation process and optimal performance.

This document provides essential information on configuring and launching Aldec AMI and instructions of using Aldec HES-DVM Proto CE and Board Compiler.

HES-DVM Proto CE is the cloud edition of Aldec's emulation and prototyping platform HES-DVM. The cloud edition is a response to the increasing demand of high-quality partitioning tools used to prepare the design prototype on multi-FPGA platforms. The cloud edition of HES-DVM is limited to prototyping flow and supports up to four (4) partitions that can be mapped to 4 high end Xilinx FPGAs (Virtex UltraScale, UltraScale+ or Virtex-7).

Aldec Hardware Emulation Solutions is a hybrid verification and validation ecosystem for hardware and software teams developing the latest SoC and ASIC designs. Partnering the latest high-capacity FPGA technology with industry leading co-emulation standards, HES allows for multiple modes of verification and validation including bit-level simulation acceleration, transaction-level emulation, Hardware prototyping, and Virtual Modeling.

Abstract: Traditional design flows postpone HW/SW integration and co-verification until the ASIC prototype is ready. With constantly shrinking time-to-market requirement this is significantly too late. If some HW bugs are identified during SW integration phase then it is impossible to make HW changes. Designers have to find sophisticated SW workarounds in order to avoid costly re-spins. Learn from Aldec how to start HW/SW integration and co-verification much earlier in your design flow along with the extensive debugging capabilities on both sides of HW and SW. Find out how to enable HW and SW design teams collaborate on a whole new level that has never been done before. Play webinar   

The Clock Domain Crossing Verification is one of the most important tasks for ASIC and FPGA design with multiple clock domains. However, there is a need to properly prepare designs for the CDC run. Most designs include the third-party IP cores, with either protected or unprotected source code. For the Clock Domain Crossing verification, it is highly important to verify the IP-based designs even though the IP contents are protected. To do so, there is a need to develop the CDC model for the protected IP core. Another problem is the CDC verification of large System-on-the-Chip designs. Due to large design size, it may be impractical to verify all the system at once. Alternatively, it make sense to use the "divide and conquer" approach, running the Clock Domain Crossing verification on leaf design modules, one by one. In order to run the CDC at system level, already verified leaf design modules has to be abstracted to the CDC models and used in the top-level run. The following webinar will show how to develop CDC models for the protected IP designs and how to run the Clock Domain Crossing verification for large designs, abstracting design block with the CDC models. Play webinar   

Together with Aldec, PLDA and Avery Design Systems, we will present and demo our newest PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA’s PCIE 5.0 XpressRich includes internal datapath automatic scaling, configurable pipelining, Rx stream mode for custom credit management, L1 PM substates, dynamically adjustable application clock frequency and clock/power gating. Avery’s APCIe-Xactor includes best-in-class Verification IP for PCIe GEN5, native SystemVerilog and UVM support, native randomization, layer wise protocol and debug tracker and 35+ callbacks for error injection. In Aldec’s Riviera-PRO you can run RTL simulation and debug, visualize simulation waveforms, view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections, and as well as use code coverage to analyze the efficiency of the UVM tests for exercising various parts of the RTL code. Play webinar