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1.1 Basics: Workspace   
A Workspace is comprised of individual designs containing resources such as source files and output files with simulation results. Learn how to create a new Workspace using the New Workspace Wizard, manage an existing Workspace, and manage the different components of the Workspace.
Active-HDL Demonstration Videos
1.2 Basics: Design Flow Manager   
The Design Flow Manager (DFM) is designed to automate and simplify the design, synthesis, and implementation processes. The interface takes the form of design flowcharts which show the design path in graphical form. Learn how to enable the DFM, choose third party vendor tools for synthesis and implementation, and how to perform each stage of the synthesis and implementation processes.
Active-HDL Demonstration Videos
1.3 Basics: Library Manager   
Learn how to create and manage user libraries, and how to utilize pre-compiled FPGA vendor libraries.
Active-HDL Demonstration Videos
2.1 Design Entry: Block Diagram Editor   
The Block Diagram Editor (BDE) is Active-HDL's tool for graphical entry of VHDL, Verilog, and EDIF designs. This is especially useful to those with HDL designs that are largely structural since it is easier to enter descriptions graphically rather than typing hundreds of source code lines. Learn how to create a new block diagram by adding new ports, adding symbols, editing symbols (pin placement, pin names, etc.), connecting symbols with wires/bus, generate HDL code, and how to create a graphical testbench.
Active-HDL Demonstration Videos
2.2 Design Entry: FSM Editor   
Learn how to create a new Finite State Machine (FSM), define ports, add new states, transitions, actions, and conditions; add multiple state machines, generate HDL code, generate a testbench, and run a simulation to trace over the transitions to observe the functionality of the state machine.
Active-HDL Demonstration Videos
2.3 Design Entry: HDL Editor   
The HDL Editor is a text editor for editing HDL source code. It contains features such as keyword coloring (VHDL, Verilog/SystemVerilog, C/C++, SystemC, OVA, and PSL), recording/playing actions, bookmarks, hyperlinks to files, creating structure groups, breakpoints, autoformat/smart indentation, etc. Learn how to create a new HDL file with the New Design Wizard and how to utilize the HDE features within that created source file.
Active-HDL Demonstration Videos
2.4 Design Entry: Mouse Strokes   
A mouse stroke is a way of performing common tasks within a window by moving the mouse in a specific pattern. Learn how to enable, perform, and customize mouse strokes.
Active-HDL Demonstration Videos
3.1 Compilation and Simulation: Compilation and Simulation   
Learn how to specify design settings for compilation (setting up debugging windows, selecting maximum optimization, etc.), how to initialize and run simulations, how to view the simulation results, and how to perform compilation and simulation with scripts.
Active-HDL Demonstration Videos
3.2 Compilation and Simulation: Compiling Vivado Simulation Libraries   
When you instantiate any Xilinx black box component in your design, Active-HDL will look for the vendor libraries to define functionality of the Xilinx Component. Before performing simulation of these designs, it is crucial not only to have the proper simulation libraries, but the correct version as well.
Active-HDL Demonstration Videos
4.1 Debugging: Introduction to Debugging    
Active-HDL provides debugging windows such as the Console, Breakpoints, Watch, Process, Call Stack, and List Viewer. Learn how to utilize the features of each window and how to use the windows to debug your designs.
Active-HDL Demonstration Videos
4.2 Debugging: Advance Dataflow   
Advanced Dataflow allows designers to explore the connectivity of an active design and analyze the dataflow among instances, concurrent statements, signals, nets, and registers during simulation. There are three display modes to help trace events propagating through the entire project: Hierarchical, Flat, and Gray. Learn how to enable settings to generate data for the Advanced Dataflow window, how to add/view modules in the Advanced Dataflow window, how to utilize context menus within the window (expand net to readers, expand net to drivers, etc.), and how to switch display modes.
Active-HDL Demonstration Videos
4.3 Debugging: X-trace   
XTrace allows users to detect and report unknown values (e.g. X, W, U, etc.) when they first appear, and before they are propagated through a design. Learn how to enable XTrace, set XTrace options, and view signals that contain unknown values.
Active-HDL Demonstration Videos
4.4 Debugging: Waveform Viewer   
The Accelerated Waveform Viewer is a high performance tool dedicated to reading and graphically presenting simulation data. Learn how to utilize advanced operations such as zooming, signal manipulations, cursors, measurements, bookmarks, browsing modes, and aliases.
Active-HDL Demonstration Videos
5.1 Coverage: Code Coverage   
Code coverage is a useful source of metric, that analyzes code execution and can help us determine the completeness of the verification effort. It helps us identify corner cases that may not be executed in your design. Code Coverage analysis tools offered by Active-HDL can provide several different types of information related to the verification process of your design.
Active-HDL Demonstration Videos
5.1 Coverage: Code Coverage    Active-HDL Demonstration Videos
5.2 Coverage: Toggle Coverage   
Toggle Coverage measures design activity within terms of changes of signal logic values and creates a reports that states whether monitored signals were initialized, experienced rising and/or falling edges, and the number of rising/falling edges during a simulation session. Learn how to collect Toggle Coverage data and view the results in XML format.
Active-HDL Demonstration Videos
6.1 Customizing & Integration: User-defined Design Management   
Starting with version 9.2, instead of source files being automatically saved to the "src" folder, users can customize the design structure for more flexible file management. Users can specify the folder name or path to store a specific file, e.g. HDL files in an HDL folder, BDE files in a BDE folder, and so on. Learn how to customize the design structure, edit/copy/share the design structure configuration file, and convert existing designs to the new structure.
Active-HDL Demonstration Videos
6.2 Customizing & Integration: Vivado TCL store Integration    
With Xilinx Vivado’s TCL store, integrating Active-HDL simulator in the Vivado work flow is easy. This combination allows users to extend Vivado’s rich synthesis and implementation tool set with Active-HDL’s high performance simulator. This seamless integration eliminates the need to manually map the source files between the two programs as this is all done in the backend.
Active-HDL Demonstration Videos
Accelerate DSP Design Development: Tailored Flows   
Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Aldec and SynthWorks: OS-VVM: Open Source - VHDL Verification Methodology   
Open Source - VHDL Verification Methodology (OS-VVM™) provides advanced verification capabilities to VHDL teams. Attendees will learn how to add functional coverage, constrained random test, and coverage driven random test to their current testbenches. OS-VVM has a straight-forward usage model that allows the addition of functional coverage, constrained random, and coverage driven random features to a testbench in part or in whole. This webinar demonstrates how the addition of Functional Coverage to testbenches is necessary - even with directed tests. Constrained Random or Coverage Driven randomization can be added when and where needed, and there is even the ability to mix directed, algorithmic, file-based, constrained random, and coverage driven random methods. OS-VVM is open source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations, and has been produced as a joint effort between Aldec and SynthWorks, both companies committed to provide continued support to VHDL design community. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
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