Recorded Webinars

When facing the challenging task of implementing Constrained Random Stimulus or Functional Coverage in their testbench, VHDL designers used to make difficult choice between "reinventing the wheel" (writing appropriate code from scratch) and "using a square wheel" (using SystemVerilog for verification). Fortunately, there is now a third option available: Open Source VHDL Verification Methodology. OS-VVM is a set of VHDL packages that provide reliable, field-tested procedures and functions handling randomization and functional coverage. This webinar will demonstrate the structure and use of OS-VVM packages, paying special attention to Smart Coverage that combines random stimulus and functional coverage to provide faster verification. Play webinar   

Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology. Like UVM, OSVVM is a library of free, open-source code (packages). OSVVM uses this library to implement functional coverage, constrained random tests, and Intelligent Coverage random tests with a conciseness, simplicity and capability that rivals other verification languages. In 2015, OSVVM added comprehensive error and message reporting (January, 2015.01) and memory modeling (June, 2015.06). With this expanded capability, this presentation takes a look at the big picture methodology progressing transactions to randomization to functional coverage to intelligent coverage to alerts (error reporting) and logs (message reporting) to memory modeling. Worried about keeping up with the latest trends in verification? With Intelligent Coverage, OSVVM has a portable, VHDL-based, intelligent testbench solution built into the library. While Accellera is still working on their Intelligent testbench based portable stimulus solution (in the Portable Stimulus Working Group -PSWG), for OSVVM it is already here. Best of all, OSVVM is free and works in all of Aldec VHDL simulators. Play webinar   

Open Source VHDL Verification Methodology (OSVVM) provides an ASIC level VHDL verification methodology that is simple enough to use even on small FPGA projects. OSVVM offers the same capabilities as those based on other verification languages. OSVVM is implemented as a library of free, open-source packages. It uses these packages to create features that rival language based implementations in both conciseness, simplicity, and capability. Looking to improve your FPGA verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Each piece is separate and can be used separately. Hence, you can learn and adopt pieces as you need them. Play webinar   

During 2020, OSVVM had 6 updates. 2021 continues this pace with a release in February, June, and July. This presentation talks about what is new. - Restructured OSVVM Release Directories (2020.07) - Scripting (2020.07) - Specification and Test Tracking (2020.05, 2020.08) - Model Independent Transactions (2020.07, 2020.10, 2020.12, 2021.06) - Virtual Transaction Interfaces (2020.12) - AXI4 Full Verification Components (2020.07, 2020.12) - AxiStream (2020.07, 2020.10) - UART (2020.07) - Documentation (2020.07, 2020.10, 2020.12, 2021.06) - Benefits of OSVVM Play webinar   

Abstract: Aldec has recently added support for the Open Verification Methodology (OVM) for SystemVerilog, which is the basis of Accellera’s forthcoming standard Universal Verification Methodology (UVM). Resulting from years of experience within lead design verification teams and EDA companies, OVM provides common building blocks and predefined mechanisms for creating reusable and expandable test environments that take full advantage of SystemVerilog and SystemC verification capabilities. This webinar introduces basic OVM concepts and shows how users with different levels of experience can rely on OVM to quickly build up a layered, coverage driven, transaction-level verification environment which can be reused across different designs. These concepts apply equally well to UVM. Aldec provides a precompiled OVM library and a SystemVerilog compatible simulator to help customers take advantage of this latest design verification technology to meet the challenge of verifying today’s complex designs. Play webinar   

Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation, collection and analysis of coverage on your designs might look challenging but with a few steps you can optimize your design flow to make the process much simpler. Many times, simulations are not run with coverage because of the long simulation run times, but if you efficiently plan your simulations and scripting, collecting coverage and analyzing the results will be a lot easier. In this webinar, we will discuss the use of verification plans, code coverage, functional coverage, coverage merging, coverage results analysis, test ranking and various scripting mechanisms to optimize simulation and reduce the time to cover all features of your design.  Play webinar   

Today’s FPGA design teams require innovative solutions that foster team productivity and enable rapid deployment at every stage of design development. Many teams are realizing the complexities of FPGA devices are increasing at a faster rate than the ability of OEM simulation tools to support them. In this webinar, we will explore the ways a vendor-independent simulation tool can help tackle the simulation and verification challenges of complex FPGA devices. Aldec's FPGA design entry and simulation solution, Active-HDL™, delivers a cost-effective, feature-packed alternative to OEM simulation tools. Join us for this webinar to learn how the industry’s most comprehensive, all-in-one platform for FPGA design development can help meet the increasing demands of the FPGA development process. Play webinar   

Presently, emulation and prototyping are essential verification and validation techniques for a SoC, ASIC, ASSP or large scale FPGA design. The FPGA based prototyping platforms are superior due to their performance and versatile connectivity. However, challenges of the multi-FPGA design setup requiring complex partitioning, I/O interconnections and mapping multiple clock domains across multiple devices drive many away from this platform. Design partitioning assistant software that can be used with either off-the-shelf or even custom made FPGA boards can significantly reduce the risk and time of the prototype bring-up. Aldec HES-DVM™ Prototyping Platform is here to aid in rapid implementation of fast and reliable FPGA prototypes. Design setup for a large multi-FPGA platform is facilitated with the DVM tool that provides partitioning utilities and can convert ASIC clocks to FPGA-proof structures, automate I/O assignment and control the timing critical paths across the board. We will demonstrate the HES-DVM prototyping flow that can be used with custom or in-house designed boards, even before the FPGA board design is finished. The results of preliminary partitioning can provide invaluable feedback to the board design team and a handful of hints on design-specific board improvements.  Play webinar   

For DAL A/B FPGAs, applicants are recommended to verify the device behavior at the silicon level (physical testing) in order to satisfy the objectives defined in RTCA/DO-254 Section 6.2.1 Verification Process. This is recommended because there are significant errors that may potentially impact safety but can only be found through physical testing. However, physical testing of the FPGA in the target board is quite challenging and not feasible in most cases. That is why both FAA and EASA allow for alternate verification means if physical tests in the target board are not feasible. Learn in this webinar a methodology that enables requirements-based physical testing with 100% FPGA I/O controllability and visibility necessary to satisfy the objectives. Play webinar   

Abstract: DO-254 is officially enforced by the FAA and other worldwide certification authorities as a means of compliance for the development of airborne electronic hardware incorporating devices such as FPGAs, PLDs and ASICs. DO-254 is rapidly becoming the de-facto standard to all safety critical applications not only in avionics but also in medical, automotive and nuclear industries. Despite of its wide applications, DO-254 is still poorly understood and implementing it remains unclear. This webinar will try to provide clarifications on the most commonly misunderstood objectives of the standard. This webinar is entirely dedicated to answer your questions related to applying DO-254 to FPGAs and PLDs. Play webinar   

The FPGA or ASIC SoC require a robust pre-silicon hardware/software co-verification platform. Virtual platforms are used successfully as high-speed simulation vehicle but only for standard components like CPU, memory, timers and the like. The challenge emerges when custom IP-core is added to the design. Developing device drivers using HDL simulation is counterproductive and testing operating system and application stack is impossible. Hybrid co-emulation of standard machine virtualizer with FPGA bridges the gap in verification environment. QEMU is a generic and open source machine emulator that supports various computer hardware architectures including Intel x86 and ARM® Cortex® families. It can be connected with the Aldec HES-DVM™ emulation platform to provide a hybrid co-emulation environment for SoC designs. We will demonstrate the latest QEMU Bridge designed to provide connection between CPU subsystem in QEMU and custom hardware IP-Core run in the HES FPGA board and mapped as PCI Express device in QEMU. We will also show how software stack GDB debugger can be used in step-lock mode with the Aldec Hardware Debugger to provide full and deterministic view of the entire SoC.  Play webinar   

Adhering to standards is key for reusability. The same applies for emulation infrastructure. Standard Co-Emulation Modeling Interface (SCE-MI) is Accellera's standard for bridging two realms: untimed (HVL, testbench on host) and timed (HDL, design in emulator). SCE-MI offers the flexibility to choose an emulation platform and become vendor independent, critical today when advanced FPGA technology allows for building fast and large capacity emulators at a fraction of the cost. Aldec’s Hardware Emulation Solutions include support for SCE-MI macro and function based interfaces. HES-DVM™ compiles and links SCE-MI infrastructure and automates design setup for custom FPGA prototyping boards. Building a robust verification environment is another challenge that Aldec supports with a library of Verification IPs that include transactors and speed adapters. Aldec provides reliable and reusable SCE-MI Verification IP blocks for standard interfaces like USB, PCIe, Ethernet. Play webinar   

The RISC-V ISA has opened tremendous opportunities creating a breeze of fresh air in the ARM dominated design houses of embedded SoC projects. We didn’t have to wait long until the first RTL implementations of the RISC-V processor were started (both open source and commercial). Currently there are several open source projects of RISC-V CPU cores. There is however a verification gap between the open source fabless design and the ones that are intended to be taped out. The HDL/RTL simulation that works well for research and open source projects is not sufficient in case of huge investments in chip fabrication where designs must be verified exhaustively. In this webinar we will present how FPGA hardware-assisted verification such as simulation acceleration, emulation and prototyping can be used at different verification stages to bridge the verification gap, increase functional test coverage and enable true hardware-software co-verification of RISC-V cores and SoCs. Play webinar   

Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably. Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and BRAM solutions in FPGA designs. XPM usage enables safe cross-clock domain transfers for control signals and data buses, providing seven clock domain crossing (CDC) capabilities such as single-bit, pulse, gray-code or handshake synchronizers. Also, Xilinx Vivado provides a CDC checker, reporting paths that start in one clock domain and pass into another. However, the capabilities of Vivado CDC checker are limited compared to advanced CDC analysis tools, while rigorous CDC verification is essential for safety and functional reliability of FPGA designs. In this webinar, we will present the methodology and design examples of efficient CDC verification for designs containing Xilinx Parametric Macros. Play webinar   

Abstract: The old technical joke says that the only truly secure information is the one that cannot be read by anybody. Traditional methods of Intellectual Property delivery for use in EDA tools were dangerously close to that 'ideal' description - secure, but almost unmanageable by both vendors and end users. Recent years brought the concept of HDL source encryption that promises well balanced mixture of security, manageability for IP and tool vendors, and total transparency for end users. This webinar presents theoretical background and practical solution of universal, inter-operable system of secure IP delivery based on source encryption. Current state of the solution is provided with an outline of the enhancements being prepared by IEEE P1735 workgroup. Play webinar   

For today’s designs the verification process may take much more time than the design phase. It happens especially for safety critical designs where extra objectives related to traceability, test in real hardware or robustness testing must be achieved. The solution is not only to make the simulation run faster but also to satisfy the safety critical objectives without extra workload. During this presentation we will show how you can speed up your verification phase and satisfy the verification objectives of DO-254 at a very short time by using our DO-254/CTS™ hardware verification platform.  Play webinar   

Assertions have been in use for over a decade for now, however, writing detailed, temporal expressions in plain SystemVerilog (SV) 2005 has been at times a demanding task for first time users. While it gets easier as users mature with SVA, the language has made it more straightforward to express complex temporals with recent additions to the standard. With SV 2012 LRM becoming freely available to all users, the adoption is expected to grow much faster. This webinar will demonstrate some of the important LTL operators added to the SVA such as until, eventually, etc. Using real-life case studies, the presenter demonstrates how these new operators can significantly reduce complexity of SVA coding. Attendees will be taken through a small, real-life protocol and shown how to break down the requirements in an “edge-by-edge” approach to coding SVA. An ethernet-like protocol case study will be used to demonstrate the value of assertions while building driver BFMs in UVM. This clearly highlights the benefit of adding assertions upfront in a project cycle by helping reduce the TB development time. Play webinar   

Presently, emulation and FPGA-based prototyping are essential verification and validation techniques for a SoC, ASIC designs and become irreplaceable in pre-silicon verification of Deep Learning Accelerator designs. Challenges of the multi-FPGA design setup like partitioning, multiplexing limited I/O interconnections and mapping multiple clock domains across multiple devices may cause significant delays in prototype bring-up and verification schedule. Design partitioning tool that can be used with either off-the-shelf or custom made FPGA boards will automate the most tedious tasks and so significantly reduce the risk. Aldec provides HES-DVM Proto toolbox with automatic design partitioning for multiple FPGAs including Xilinx Virtex UltraScale XCVU440. In this webinar we will demonstrate how to compile and partition an open source design of Deep Learning Accelerator into 6 FPGAs in 6 steps which are fully automated. Play webinar   

Hardware and Software teams both play a key role in developing the latest SoC designs. Early access to the emulation platform allows both teams to work concurrently with one another, enabling hardware/software co-design and co-verification. HES-DVM™ allows using FPGA boards in different modes like simulation acceleration, transaction-level emulation or integrated with virtual platforms. Another option is in-circuit emulation with speed adapters that provide a high-speed hardware interface. This complemented with powerful RTL source level debugging options make emulation easier than ever before. Play webinar   

Smart IoT devices and AI-driven autonomous machines are set to become commonplace in the near-future. Most will incorporate an ARM-based System-on-Chip (SoC) that has both hardware and software components; that should be verified together. Often, software is verified separately from hardware either due to the lack of accurate ARM hardware model or simulation bottleneck. An emulation platform combining reconfigurable FPGA logic with ARM processors bridges the gap. However, while FPGA vendors have mixed-technology platforms, like Xilinx Zynq, they contain insufficient FPGA logic elements to implement contemporary SoC designs. In this webinar we will demonstrate how to connect Xilinx Zynq MPSoC and its ARM Cortex A53/R5 processors with the largest Xilinx UltraScale FPGA. During a live demo, Aldec’s HES-DVM emulation platform will be connected with a TySOM-3 board, and we will show you how to combine ARM cores from Zynq with the rest of the SoC implemented in Ultrascale FPGA utilizing AMBA AXI and MGT based chip-to-chip interconnect. Finally, we will demonstrate the hardware and software debugging capabilities of such a hybrid emulation platform.  Play webinar