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Transaction Level Co-Emulation with Virtual Platforms   
Co-Webinar with Imperas® Abstract: Virtual platforms play a significant role in system level development, but require integration with ultra fast emulation systems for HW/SW co-verification. In this webinar we will introduce the new integration of Aldec's Transaction Level Emulation System with Imperas' OVPsim virtual platform simulator. Hardware and software design teams are now able to implement virtual models of processors, memory and peripheral modules while the RTL modules run in the emulator board. This integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.  Play webinar   
Riviera-PRO Recorded Webinars
Transaction Level Visual Debugging   
Abstract: It’s been obvious for some time that today’s SOCs cannot be verified solely using traditional RTL modeling techniques. Only recently has the EDA industry begun to widely adopt the concepts of TLM, although the general idea has been around since 1960s. Though relatively new to our industry, transaction-level environments have already become mature methodologically (UVM), however adequate debugging and visualization capabilities remain at a somewhat basic level. Aldec is an EDA vendor that understands the importance of this topic and actively develops the right tools to enable a smooth flow for convenient debugging at a level of abstraction higher than traditional RTL. Play webinar   
Riviera-PRO Recorded Webinars
Universal VHDL Verification Methodology (UVVM) – The standardized open source VHDL testbench architecture   
The European Space Agency (ESA) is currently sponsoring further development of UVVM. For an FPGA design we all know that the architecture – all the way from the top to the micro architecture – is critical for both the FPGA quality and the development time. It should be obvious to any experienced designer that this also applies to the testbench. Most FPGA designs are split into stand-alone modules – for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities, and they are normally accessed from a CPU via a standardized register interface, which acts as an abstraction layer. This abstraction allows a safe and efficient control of the complete FPGA. Such an approach should also be used for the verification environment - to simplify the testbench architecture and the control of the interfaces. This way the verification structure will mirror the design structure, allowing the best possible overview, readability, maintainability and reuse. There is however nothing even close to a standard on how to build the testbench architecture, how to access the verification components, how to control them, or how to extend them for more complex functionality. UVVM provides a very simple and powerful solution for all of this - and has in fact standardized the testbench architecture, the microarchitecture of the verification components and their command/status interface, a set of common commands, debugging support, etc. This makes it possible for the whole VHDL community to make verification components that have the same architecture, can be integrated the same way, debugged the same way and controlled the same way. Thus, verification components may be shared easily within the VHDL community, allowing designers to build their own test harness much faster than ever before – using a mix of their own and 3rd party VHDL verification components.  Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Use Python and bring joy back to verification   
cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. cocotb encourages the same philosophy of design re-use and randomized testing as UVM, however is implemented in Python rather than SystemVerilog. With cocotb, VHDL/Verilog/SystemVerilog are normally only used for the design itself, not the testbench. In this webinar we will introduce cocotb and show how to get started with a small design using Aldec’s Riviera-PRO. We will also show a more complex example, giving you a taste how cocotb could add value -- and joy! -- to your next verification project. Play webinar   
Riviera-PRO, HES-DVM, HES™ Boards, TySOM™ EDK Recorded Webinars
Using ALINT-PRO to Verify Clock Domain Crossing Issues in FPGA designs   
The Clock Domain Crossing Issues cause functional instability of FPGA designs. It is extremely hard to understand the cause of such issues. Even though design is working perfectly in Functional simulations, it may still fail during Lab Testing. Recently, FPGA vendors (such as Xilinx) introduced certain amount of CDC checks into their development environments. However, these checks are not sufficient and has to be enhanced with the third-party CDC verification tools. ALINT-PRO provides smooth and practical solution for the FPGA Projects Code Linting and enhanced Clock Domain Crossings Verification. The automated code conversion allows FPGA designers to load complex FPGA projects into the ALINT-PRO environment in seconds. The enhanced Clock Domain Crossing Verification with ALINT-PRO is able to reveal hard-to find issues causing functional instability of FPGA designs. Current webinar explains this methodology and demonstrates it on the real-world FPGA design.  Play webinar   
ALINT-PRO Recorded Webinars
Using OVL for Assertion-Based Verification of Verilog and VHDL Designs   
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement assertion-based verification of their design. Finally, OVL supports any HDL language (Verilog, SystemVerilog, VHDL), enabling assertion-based verification with any simulation tools. In this webinar, we will present practical guidance on how to start using Open Verification Library (OVL) in design and verification process. We will provide various code examples to demonstrate how to efficiently use OVL for Verilog and VHDL design verification. Static formal and emulation-based verification methods using OVL will be outlined as well.  Play webinar   
Riviera-PRO Recorded Webinars
UVM-based Verification of Custom Instructions with RISC-V Cores   
By integrating Aldec’s Riviera-PRO™ with Codasip’s Studio™, verification of RISC-V CPU custom instructions at the RTL implementation level becomes an incredibly powerful platform for RISC-V processor deployment. In this presentation, we will show in Studio, how users can describe the RISC-V architecture and add custom instructions using CodAL high level language, modify the pipeline, configure random instruction generator, auto-generate the HDK, SDK, RTL implementation and C++ reference model and UVM environment, start RTL simulation, setup breakpoints and debug. We will then show in Riviera-PRO, how users can run RTL simulation and debug applications and core architecture, inspect simulation waveforms, use the UVM Graph & Toolbox to view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections between them, giving the user an overall perspective of the testbench architecture and the dataflow. We will also show how you can collect and analyze both functional coverage and code coverage.  Play webinar   
Riviera-PRO Recorded Webinars
UVM for FPGAs (Part 1): Get, Set, Go – Be Productive with UVM   
The Accelera Universal Verification Methodology (UVM) became an IEEE standard published as IEEE 1800.2 – IEEE Standard for UVM Language Reference Manual (LRM). UVM has been the predominant verification methodology for ASIC designs for many years and has recently gained popularity and usage with FPGA designs. UVM can improve interoperability and reduce the cost of reusing and integrating IPs. Think of lego-like verification process based on pre-built pieces/components/IPs - that’s precisely what UVM provides to design teams. Learning UVM can take a long time especially if one were to go by the extensive information provided in the LRM. In this webinar, we will cover the basics of UVM and how to get more productive with tips, tricks and techniques. We will walk through basic UVM features from a typical end-user perspective and learn to build a small testbench with UVM.  Play webinar   
Riviera-PRO Recorded Webinars
UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM   
Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed validation in the lab simply do not scale up any longer. Even to map a large logic design to a modern-day FPGA takes many hours. FPGA verification is more and more moving towards simulation-based techniques and requiring more advanced verification capabilities such as those used in ASICs. In the field of ASIC design verification, UVM is the de-facto standard in developing testbenches, stimulus and coverage. While there is nothing ASIC-specific in UVM, the sheer complexity, transaction level methodology and object-oriented approach keep many un-initiated FPGA designers away from adopting UVM. In this webinar, we will share our experience in making UVM adoption easier for FPGAs. We will show how VHDL designs can use UVM testbenches with great ease. We will demonstrate how simple TCL based apps can help FPGA designers to quickly create a template for a given design. The availability of such apps will expedite UVM adoption in the FPGA community. We will also talk about certain unique challenges in FPGAs for space applications such as error injection testing and how UVM can be customized in solving some of these challenges. Play webinar   
Riviera-PRO Recorded Webinars
UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help   
The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom IPs with memory-mapped registers. While these IPs vary in size and complexity, they are all configurable via registers that are typically composed of a field name, field width, access type, default values and policies. RTL simulations for verifying these IPs especially in various configurations require the use of hierarchical register models - creating them is not a trivial task and require a common framework and automation. Play webinar   
Riviera-PRO Recorded Webinars
UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates   
Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020. UVM is currently the most adopted industry standard in VLSI/Semiconductor design world. With decades of proven Best Known Methods (BKMs), UVM brings productivity to every team in short span of time. In this webinar, we will walk through UVM evolution over a decade in Accellera and then in IEEE since 2017. Some of the changes are backward incompatible and needs attention from users while migrating. Play webinar   
Riviera-PRO Recorded Webinars
UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV   
This presentation showcases the RTL simulation of the SV/UVM testbench of the Ibex core, a 2-stage in-order 32b RISC-V processor core, that is designed to be small and efficient. This SV/UVM testbench uses the open source RISCV-DV random instruction generator, which generates compiled instruction binaries. These binaries are loaded into a simple memory model which then stimulates the Ibex core in Riviera-PRO to run this program in that memory. The ibex core simulation trace log is compared against a golden model generated by an Instruction Set Simulator (ISS) trace log to check for correctness of execution. The testbench is created based on its usage of the RISCV-DV random instruction generator developed by Google. There are two memory interface agents that are instantiated within the testbench, one for the instruction fetch interface, and the second for the Load-Store Unit (LSU) interface. These agents which run the slave sequences wait for memory requests from the core, and then grant the requests for instructions and data. There is also an Interrupt Interface Agent which is used to drive stimulus onto the Ibex core’s interrupt pins randomly during test execution. The testbench instantiates a single instance of the memory model that it loads the compiled assembly test program into at the beginning of each test. This serves as a unified instruction/data memory that processes all requests from both of the memory interface agents. The tests located in the Tests and Sequence Library are the main sources of external stimulus generation and checking for this testbench, as the memory interface slave sequences simply serve the core’s memory requests.The tests are all extended from core_ibex_base_test, and manage the entire flow for a single test, from loading the compiled assembly binary program into the testbench memory model, to checking the Ibex core status while the test is running and handling test timeouts. The sequences here are used to drive interrupt and debug stimulus into the core. The goal of this testbench is to fully verify the Ibex core with 100% coverage. Riviera-PRO can be used to examine the coverage results, visualize the UVM environment and aid in the debug of the verification environment. Play webinar   
Riviera-PRO Recorded Webinars
UVVM - A game changer for FPGA VHDL Verification   
Aldec and Bitvis present a complete verification solution for VHDL users consisting of a high-performance RTL simulator and a component-oriented VHDL environment.

In this webinar, we introduce UVVM methodology with VHDL Verification Components for a ultra-fast, ready-for-reuse simulation solution. Attendees will learn more about the powerful Riviera-PRO User Interface with robust debugging and analyzing capabilities for validation of design under test simulation results.  Play webinar   
Riviera-PRO Recorded Webinars
UVVM steps up a gear: A review of some of the new features in this standardized VHDL verification methodology    
The verification of large or complex designs targeted at FPGAs is time consuming. However, with a good testbench architecture the workload can be greatly reduced. UVVM provides an ideal VHDL testbench architecture as well as a good reuse structure. Entry-level UVVM is easy, even for beginners. For more advanced verification, the standardized verification components, the high-level software-like commands and other features will allow complex verification scenarios to be handled in a structured and understandable way. UVVM is open source and provides a ‘kick-start’ testbench with BFMs and verification components for UART, SPI, AXI-lite, AXI stream, Avalon MM, Avalon stream, I2C, GPIO, SBI, GMII and Ethernet. UVVM has been significantly updated through the ESA’s (European Space Agency’s) UVVM extension project. We have previously released the Scoreboard, and now lots of other new functionality has also been added. The most important of these new functions are Activity Watchdog, Error Injection, Monitor, Hierarchical VVCs and Specification Coverage. This presentation will provide an introduction to UVVM Utility Library, BFMs and VVCs, and then go through the new features and explain how they will help you make a better testbench and, in doing so, shorten your overall project development times. The usage of UVVM is exploding, and all the new features are already greatly appreciated by the VHDL community. UVVM is the best possible solution for all the features needed for the most efficient FPGA development and high-quality products: - The best possible Overview, Readability, Maintainability - The simplest possible control of large or complex testbenches - Unique Reusability Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Validation and Verification Process for DO-254   
Requirements are central to the development process described in DO-254. The Validation and Verification Process ensures that requirements are correct, complete, verifiable, unambiguous, logically consistent, the design data correctly implements the requirements and the final FPGA functions as intended as defined in the requirements. Learn in this webinar the objectives, purpose and methods of Validation and Verification. The webinar will describe the validation and verification process and techniques for selected example requirements. Play webinar   
DO-254/CTS Recorded Webinars
Verifying Finite State Machines with Aldec Products   
Finite State Machines play a key role in design functionality being an essential part of design control logic. FSM-related bugs have direct influence on core design functionality, and usually there are no workaround solutions to the FSM-related issues. Therefore, designers have to pay special attention to the correct design and verification of the FSM code. Static FSM verification methods complement functional simulation to achieve flawless FSM functionality. Static code styles and naming conventions checks help designers to develop clear and concise FSM code as well as enforce the company-specific FSM development styles and restrictions. The recently added FSM viewer allows designers to extract and explore FSM structures in existing RTL code for the debugging, back-annotation and documentation purposes. Play webinar   
ALINT-PRO Recorded Webinars
Verifying Resets and Reset Domain Crossings   
Correct and clean reset strategy is essential for multi-million gate FPGA and ASIC devices. The possibility to start device operation from a potentially wrong state may cause malfunctions of hardware designs. Also, asynchronous resets may cause metastability effects, causing design malfunction and overheating due to increased power consumption. This webinar will describe Reset Structures and Reset Domain Crossings verification methodology and rules, demonstrated on demo designs using ALINT-PRO. The methodology behind ALINT-PRO includes careful static reset verification and ensuring valid design functionality (after resets de-assertion and an absence of metastability issues during reset assertion).  Play webinar   
Riviera-PRO, ALINT-PRO Recorded Webinars
VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment   
IEEE 1076-2019, fondly referred to as VHDL-2019, was approved by IEEE RevCom in September 2019 and published in December 2019. The effort was supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing. Language changes were use model driven and had multiple opportunities to be pruned from implementation. The process started with a discussion of feature requests. Feature requests were then voted on and ranked. High ranked features were discussed and developed into proposals. Proposals were required to provide use models to affirm their worth and validity. Proposals were then developed into language change specifications (LCS). The entire process was driven by volunteers – and again almost all were users. Volunteerism added another level of scrutiny to each request and/or proposal. If no one was willing to write a proposal or an LCS for an item, then no matter how high the feature or proposal was ranked, it failed to be worthy of being implemented. In Part 1 of VHDL-2019: Just the New Stuff series, we will explore: Interfaces Conditional Compilation File IO Updates Environment Package Updates Interfaces allow abstract connections between designs. Ever wanted to encapsulate all signals of an interface into a single record only to be confounded by not being able to specify the direction of elements of the record? Well now you can. Conditional compilation. Users have requested this numerous times. Finally done! The File IO updates include file open state, rewind, and file position. The Environment package updates include Directory operations, access to Date and Time, and access to environment variables.  Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
VHDL-2019: Just the New StuffPart 2: Protected Types and Verification Data Structures   
In this second webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL's protected type capabilities. Protected types simplify and abstract the construction of data structures. As such they are the enabling feature that makes it possible to create VHDL verification methodologies that are competitive with SystemVerilog + UVM, such as Open Source VHDL Verification Methodology (OSVVM). OSVVM uses protected types to create functional coverage, Intelligent Coverage random test generation, messaging (logs), unified error reporting (alerts/affirmations), and verification data structures (Memory Models, FIFOs, and Scoreboards). We will start the presentation with an overview of protected types and how they work. This will help all participants understand the impact of the changes. The balance of the presentation is dedicated to covering the changes and why they are important. Some of the updates discussed during this presentation will be: Protected Types with Generics Composites (arrays) of Protected Types Pointers to Protected Types Composition with Protected Types Protected Types on Entity Interface Protected Type Methods with File Types Protected Type Methods with Access Types Functions with Protected Type Parameters These new features allow libraries like OSVVM to take the next step in advancing VHDL’s verification capabilities. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
VHDL-2019: Just the New Stuff Part 3: RTL Enhancements   
In this third webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL's RTL coding capabilities. For a long time, VHDL was more verbose than other languages, however, much of that was fixed with VHDL2008. At the completion of VHDL-2008, VHDL was as concise as Verilog/SystemVerilog. VHDL-2019 continues working to make VHDL more concise and expressive. Two big RTL enhancements VHDL-2019 added are VHDL Interfaces and conditional compilation. This was covered in the Part 1, “VHDL-2019 Interfaces, Conditional Analysis, File IO, and The New Environment.” This presentation furthers the discussion of RTL enhancements and covers the following: Optional trailing semicolon at the end of interface list All interface lists are ordered Allow functions to know the output vector size Inferring signal and variable constraints from initial values Conditional expressions in object declarations Conditional return Component declaration syntax regularization Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
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