Play Webinar

Title: OS-VVM: High-Level VHDL Verification

Description: When facing the challenging task of implementing Constrained Random Stimulus or Functional Coverage in their testbench, VHDL designers used to make difficult choice between "reinventing the wheel" (writing appropriate code from scratch) and "using a square wheel" (using SystemVerilog for verification). Fortunately, there is now a third option available: Open Source VHDL Verification Methodology. OS-VVM is a set of VHDL packages that provide reliable, field-tested procedures and functions handling randomization and functional coverage. This webinar will demonstrate the structure and use of OS-VVM packages, paying special attention to Smart Coverage that combines random stimulus and functional coverage to provide faster verification.

Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours.

If you already have an Aldec account, please Sign In below to download the file.