How does HES-DVM handle simulation memory models?


HES-DVM provides a set of features and interfaces to map simulation memory models onto on-chip or on board RAM resources.

This feature allows offloading the usage of PC’s system memory during design simulation and considerably increasing the design simulation acceleration factor. HES-DVM maps design memory instances either to FPGA internal block RAM resources (small volumes) or to external on-board/daughter board DDR-SO-DIMM storage (large volumes).

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.