How does HES-DVM handle gated clocks in my design?


HES-DVM automatically detects both internal and external clocks in the design, and converts post-synthesis design netlist to FPGA safe netlist where clock gates are changed to clock enables. This makes an FPGA safe design automatically without any user interaction.

The Clock Conversion algorithm has been proven in many industrial and research projects and has been patented by Aldec: U.S. Patent 7,003,746 B2.

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