How does HES-DVM handle simulation memory models?


HES-DVM provides a set of features and interfaces to map simulation memory models onto on-chip or on board RAM resources.

This feature allows offloading the usage of PC’s system memory during design simulation and considerably increasing the design simulation acceleration factor. HES-DVM maps design memory instances either to FPGA internal block RAM resources (small volumes) or to external on-board/daughter board DDR-SO-DIMM storage (large volumes).

Printed version of site: