Compiling Xilinx Vivado Simulation Libraries for Active-HDL

Introduction

This document describes how you can compile simulation libraries in Xilinx™ Vivado Design Suite to be used in Active-HDL.

When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation. Thus, before performing simulation of the design that contains Xilinx components in Active-HDL, you should attach the proper simulation libraries.

You can either use pre-compiled simulation libraries provided by Aldec (libraries can be downloaded from Aldec's website) or you can compile them yourself in the Xilinx Vivado Design Suite then attach the compiled libraries into Active-HDL.

Requirements and Limitations

This application note assumes that you have Xilinx Vivado Design Suite 2019.2 or later and Active-HDL 11.1 or later properly installed and licensed.

Compiling simulation libraries

You can either use the compile_simlib command or the Compile Simulation Libraries wizard that simplifies compiling simulation libraries. With these tools, you can compile all IP core libraries included in the Vivado IP Catalog and the following basic Xilinx Vivado simulation libraries:

  • UNISIM

  • UNIMACRO

  • UNIFAST

  • SIMPRIM (Verilog Only)

  • SECUREIP (Verilog Only)

  • XILINX_VIP

  • XPM

You can find detailed description of these libraries in the following document: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug900-vivado-logic-simulation.pdf

Using the Compile Simulation Libraries Wizard

  1. Open Vivado.

  2. Go to Tools | Compile Simulation Libraries.

    Figure 1: Accessing the Compile Simulation Libraries.

  3. The Compile Simulation Libraries will open.

  4. Select Active-HDL under Simulator. Select the desired language and libraries.

    Figure 2: Compile Simulation Libraries: Simulator, Language and Library selection.

  5. Under the Compiled Library Location, select the directory where you want the compiled libraries to be saved. Under the Simulator Executable Path, provide the path to the directory containing the avhdl.exe file in the Active-HDL installation directory.

    Figure 3: Compile Simulation Libraries: Compiled library location and Simulator executable path.

  6. By default, all the IP modules available in the Vivado IP Catalog are selected for compilation. You can change that behavior by clearing the Compile Xilinx IP check box. When cleared, only the basic simulation libraries are compiled. You may also want to enable recompilation of libraries already present in the output directory. To do so, select the Overwrite the current pre-compiled libraries check box.

    Figure 4: Compile Simulation Libraries: Compile Xilinx IP and Overwrite the current pre-compiled libraries.

  7. When you have specified all of your settings, select Compile.

    Figure 5: Compile Simulation Libraries: Compile.

  8. Once the compilation is completed, you should see the compilation summary in the Tcl Console similar to the one in the picture below:

    Figure 6: Tcl Console: Compilation Summary.

Using the compile_simlib command

  1. In Vivado Design Suite, execute the following command from the Tcl Console:

    compile_simlib -simulator activehdl -simulator_exec_path <Active-HDL installation folder> -family all -language all -library all -dir <output_folder>

    where:

    <output_folder>

    Specifies a path to the directory where you want compiled libraries to be saved.

    <Active-HDL installation folder>

    Specifies a path to the bin folder inside Active-HDL installation folder.

    NOTE: It might be required to put the path to the Active-HDL executable in quotes or curly brackets as the compile_simlib command does not accept spaces within a path.

    For example, the command may look as follows:

    compile_simlib -simulator activehdl -simulator_exec_path {C:/Aldec/Active-HDL 11.1/BIN} -family all -language all -library all -dir {C:/Aldec/Xilinx_Lib}

    Figure 7: Executing compile_simlib command from the Vivado Tcl Console.

    The above command will compile all simulation and IP libraries written in both languages (VHDL and Verilog) for all devices available in Vivado. To disable compilation of IP Core libraries and compile only Xilinx simulation libraries, invoke the compile_simlib command with the -no_ip_compile argument. You may also want to disable recompilation of libraries already present in the output directory by issuing the -force argument. To obtain the complete list of available arguments, type compile_simlib -help in the Vivado Tcl Console.

  2. Once the compilation is completed, you should see the compilation summary in the Tcl Console similar to the one in the picture below:

    Figure 8: Library Compilation Summary.

    The output directory (specified with the -dir argument) will contain the library.cfg configuration file and the folders with pre-compiled libraries.

Attaching Compiled Xilinx Libraries into Active-HDL

After generating the compiled Xilinx libraries, they have to be attached into Active-HDL. You can either use the amap command or the Attach Library wizard to add required libraries. If you are using Active-HDL as the default simulator in Xilinx Vivado 2017.4 or later, you can attach the libraries within that environment.

Using the Vivado Environment

  1. In Vivado, specify the path to the directory with the compiled libraries in the Compiled library location field available in the Project Settings | Simulation category of the Settings window.

  2. Select the Use precompiled IP simulation libraries check box in the Project Settings | IP | Simulation category of the Settings dialog box. If this option is enabled, all the required libraries such as the precompiled IP simulation libraries and the xilinx_vip and xpm libraries are included as mappings in the generated macros so they are not recompiled when invoking the Active-HDL simulator.

    NOTE: If the mappings are not successfully created, check whether the entries in the library.cfg file are specified correctly and the physical libraries exist in the specified locations.

  3. Set up and launch Active-HDL as the default Xilinx Vivado simulator. For more information, refer to Starting Active-HDL as Default Simulator in Xilinx Vivado 2017.4 or Later.

Using the Attach Library Wizard

  1. Open Active-HDL. Click Cancel when it prompts to open a workspace.

  2. Go to Library | Attach Library...

    Figure 9: Accessing the Attach Library.

  3. Select the location of the compiled Xilinx libraries, then select the *.lib file of the selected library. If you are using Active-HDL as the default simulator in Xilinx Vivado, make sure that the Attach as Global Library check box is selected. Click Open.

    Figure 10: Attach Library: Library selection.

  4. Repeat the steps 2-3 for every library that needs to be attached. Verify that the libraries are attached properly under Library Manager.

    Figure 11: Library Manager: Verifying attached Xilinx libraries.

Using the amap Command

  1. In the Active-HDL Console window map the libraries using the amap command. If you are setting up Active-HDL as the default simulator in Xilinx Vivado, map the libraries globally using the -global argument:

    amap -global <Logical Name> "<Lib File Path>"
    

    where:

    <Logical Name>

    Specifies the logical name of the library.

    <Lib File Path>

    Is the name of the library index file with the full path and the *.lib extension.

    NOTE: The path to the *.lib file is contained within quotes because the amap command does not accept spaces within a path.

    For example, the command may look as follows:

    amap -global unisim "C:\Aldec\Xilinx_Lib\unisim\unisim.lib"
    

    Figure 12: Executing amap command from the Active-HDL Console.

    You can find information about the amap command by typing amap -help in the Console.

  2. Repeat the step 2 for every library that needs to be attached. Verify that the libraries are attached correctly under Library Manager.

Using the amap Command in VSimSA

In the VSimSA environment, you can add multiple libraries with a single amap invocation:

amap -link <directory>

where:

<directory>

Directory containing the libraries and library.cfg file generated by Vivado.

This will map the libraries locally to the library.cfg file from the current VSimSA directory.

Conclusion

In order to simulate Xilinx Vivado designs in Active-HDL, Xilinx simulation libraries are required. You can either use pre-compiled libraries provided by Aldec or you can compile the libraries yourself in Vivado Design Suite. After compiling the libraries in Vivado, they have to be attached into Active-HDL in order to run the simulation.

If you have difficulty compiling or using the libraries, please contact Aldec Support through the customer portal.

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