Performing Functional Simulation of the system created with Qsys in Active-HDL


This document describes the steps required to run functional simulation of Altera Qsys design in Active-HDL. The Qsys tutorial design example is used to demonstrate the flow.

Requirements and Limitations

This application note assumes the following:

  1. You have the following software installed and licensed:

    • Altera Quartus® II version 14.1 or later, and all necessary devices from Altera

    • Active-HDL 10.1 or later

  2. Make sure that the VHDL and Verilog libraries are installed from the Aldec website that corresponds to the version of Quartus that you are using.

  3. You have downloaded the Qsys tutorial design example ( used in this application note. You can download it from the Qsys Tutorial Design Example web page.

  4. You have followed the instructions provided in chapter 5 of the Qsys System Design Tutorial and have generated the rivierapro_setup.tcl script.

Running the QSYS Design Simulation

  1. Once you generate the simulation models in Qsys, the rivierapro_setup.tcl script is generated in the tt_qsys_design/simulation_tutorial/ pattern_generator/testbench/ pattern_generator_tb/simulation/aldec folder.

    Figure 1. rivierapro_setup.tcl script

  2. Open Active-HDL. Change the location to point to the rivierapro_setup.tcl script. Execute the following command from the Console:

    cd <path to the design>/tt_qsys_design/simulation_tutorial/pattern_generator/testbench/pattern_generator_tb/simulation/aldec

    where <path to the design> points to the folder where you extracted the tt_qsys_design_zip archive.

  3. Open the rivierapro_setup.tcl script. Execute the following command from the Console:

    open -do rivierapro_setup.tcl

    This script sets up all necessary environment variables, compiles Altera libraries, compiles design files, and initializes the simulation. The script can be executed as is, or you can modify any of the commands in it according to your needs.

    Table 1, shown below, provides the description of the alias commands used in the script. The commands described below are the alias commands that are defined in the rivierapro_setup.tcl script:

    Table 1- Command aliases


    for compilation device library files


    for compilation the design files


    for elaboration top level design (top level design is defined in script by TOP_LEVEL_NAME variable)


    for elaboration the top level design with optimization disabled (with -dbg -o2 options)


    for compilation all the design files and elaboration the top level design


    for compilation all the design files and elaboration the top level design with optimization disabled with -dbg -o2 options)

  4. Modify line 33 as follows and save the script:

    set QSYS_SIMDIR "../../.."
  5. Run the script. Execute the following command from the Console:

    do rivierapro_setup.tcl

    Once the script is executed, the new design will be created and activated.

    Figure 2. New Design in Active-HDL

  6. Execute the dev_com command from the Console.

    NOTE: If you already have Altera libraries installed, you can skip this step.

    This will compile the following libraries:

    • altera_ver

    • lpm_ver

    • sgate_ver

    • altera_mf_ver

    • altera_lnsim_ver

    • cycloneiii_ver

  7. Execute the com command from the Console. This will compile design source files

  8. Execute the elab command from the Console. This will initialize the simulation.

  9. Run the simulation by executing the run 40us command from the Console.


You can instantiate your top module (which contains your Qsys module) inside the Testbench VHDL file generated in order to simulate your entire design.


Altera Qsys designs can be successfully simulated in Active-HDL. To get detailed information about creating a system with Altera Qsys, refer to the following link:

If you have difficulty simulating the Qsys design in Active-HDL, please contact Aldec Support via customer portal

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