Traceability to HDL Sources in Questa®


The Spec-TRACER tool suite also offers traceability to HDL design sources created and managed in Questa. Simulations are done within the Questa environment and the simulation log files are parsed to Spec-TRACER via Active-HDL. Spec-TRACER can automatically create an Active-HDL design based on the HDL design structure and files hierarchy preserved in Questa. This application note provides detailed information on how traceability to HDL sources in Questa is performed in Spec-TRACER.

Active-HDL Design Plugin

Within the Spec-TRACER environment, there is an Active-HDL Plugin (). This plugin allows users to automatically create an Active-HDL design based on the design sources in Questa. When users click on the icon, the following window appears:

Create Active-HDL Design Window

The Create Active-HDL Design window, allows users to specify various project settings for a given design.

In this section of the Create Design window, users can specify:

  • Project Name: This is the name of the given project

  • Project Path: The path to the project where all of the project information will be stored i.e. source files.

  • Active-HDL Path: The path to the avhdl.exe which is located in Active-HDL Installation <version>/bin.

    NOTE: Be sure the Active-HDL version is 9.2 SP1 Update2 or later.

  • Configuration: Users can utilize the DO-254 Configuration which has everything predetermined, or a New Configuration that is completely user defined.

The Block Selection section allows the users to specify which blocks the FPGA Requirements and Test Scenarios are stored. The selections are chosen by default when the DO-254 Configuration is selected. If a user selected New Configuration, the Blocks field will show all of the blocks available within the design. The user will need to manually select the block that stores the FPGA requirements as well as the block that stores the Test Scenarios.

The Tags Construction Rules section allows users to specify how the HDL tags will be labeled within the Active-HDL environment. For example, in the Prefix field, HDL tags will have a prefix of HDL_, and Testbench tags will have a prefix of TB_. The Counter field allows users to specify where to start counting the tags i.e. 000. The Postfix field allows users to add any additional information to the tags if necessary.

The Test Results section allows users to specify details for capturing simulation results and storing them into a Spec-TRACER repository. The Attribute field displays the list of enumerated attributes that are available in the design. The user chooses the Attribute that stores the test scenario status i.e. Test Status. The Test RegExp fields allow the user to define the expression that is used to search for test scenarios.

The Store Settings section allows users to specify which block and motive that the HDL and Testbench tags should be stored. If a user has selected New Configuration, the user will need to manually select the appropriate blocks and motives. Users can also specify whether to create an Empty Design or create a design and Attach Existing Files.

Creating a Design and Attach Existing Files

In the Store Settings section of the Create Active-HDL Design window, users can select the option Attach Existing Files to create a design with existing sources. For this section, an example from Questa will be used.

  1. Select the Attach Existing Files option in the Store Settings section. This will activate the Add Files button.

  2. Click on Add Files. This will open the Add Files window.

    NOTE: The Keep Folder Structure option keeps the same structure as the Questa folders in the new location.

  3. Click on Add Files and select all of the relevant source files.

  4. After clicking Select, the files can be observed in the Add Files window.

  5. Click Create to create the design.

  6. Active-HDL will open with the created design and attached files.

  7. From the Active-HDL environment, users can now preform traceability activities with the HDL design and testbench sources. The user only needs to connect to the related repository and project. For more information on traceability see the DO-254 Requirements Traceability Tutorial and How to Trace to an HDL Design and Testbench.

Sending Simulation Results from Active-HDL to Spec-TRACER

Simulations are performed in the Questa environment. After simulations are completed in Questa, users can send the simulation results from Active-HDL to Spec-TRACER using the Capture Simulation Results feature.

NOTE: The images below are examples taken from the interrupt_controller project from the sample Spec-TRACER repository.

When users click on the icon, the Simulation Results Exporting window appears.

Users need to add the related simulation log file that is created when a simulation is performed in Questa. Once the file is added, clicking Search will display the test scenarios along with their status.

Clicking Apply will export the data to the Spec-TRACER tool.

Simulation Results in Spec-TRACER

The exported simulation results from Active-HDL can be displayed in Spec-TRACER by using the Items Views menu.

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