Installation of Pre-compiled Vendor Libraries for Riviera-PRO

Overview

Aldec provides pre-compiled vendor libraries for the major FPGA vendors. Both Windows and Linux versions of the vendor libraries are provided. To download a vendor library, pre-compiled for Riviera-PRO, you will need to log into your user account at www.aldec.com, proceed to DOWNLOADS page, accept the terms and conditions, select Riviera-PRO from the list of products, select the release number and the OS platform and you will be taken to the download page with the vendor libraries listed on it. Download the libraries of your FPGA vendor and store them on your disk.

Unzip/untar the downloaded library file

  • The library files from the same vendor are grouped in their separate directories. The default location where to put the library files is the vlib folder inside the Riviera-PRO main installation directory. You can either copy them to this folder or put them in any other convenient location.

Registering the libraries in Riviera-PRO

Once the libraries have been extracted from the archive file and copied to their destination folder, e.g. the vlib folder under the main installation folder, those libraries have to be mapped, i.e. registered with Riviera-PRO, which enables using them in your designs.

  • Preferably you should map your libraries as global so that they can be accessed by any design from any location.

  • Use the following amap command from within Riviera-PRO (or vmap command from the OS shell):

    amap <-global> <library_name> <physical_Library_location>
    

    Example:

    amap –global unisim xilinx_libs/unisim/unisim.lib
    

All library mappings are registered in <Riviera-PRO/vlib/library.cfg> file. You may open this file in the read mode to visually make sure all libraries are listed.

Using the vendor libraries

Once the vendor libraries have been registered or mapped you can start compiling your design files that reference those libraries. Note, that in case of Verilog you also need to point to the vendor libraries.

  • if you compile your design files using GUI menu, then before you start compilation go to your Design Properties, then navigate to Compliation | Verilog | Entries , and select Show enries for to Verilog libraries, then using Add new button select from the list of vendor libraries that you have registered above. When done, click on OK to close this dialog window.

  • if you are using the script/batch mode, then use:

    alog -work <work_lib> -l <vendor_lib> <list_of_vlog_files>
    

In case of VHDL no library pointing is necessary, since the libraries are being explicitly referenced in the library clause inside the source file.

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