Installing and Simulating Xilinx SmartModels in Active-HDL

Xilinx has stopped using SmartModels (a.k.a. Swift models) for the hard IP cores starting with the ISE 11. With ISE 11 and later all SmartModels were replaced with the SecureIP models. If you are using any hard IP cores except PowerPC 405 for Xilinx devices please use SecureIP simulation library provided by Aldec. If you are using PowerPC 405, Xilinx does not provide PowerPC405 SecureIP model for Aldec. So your choice is either to upgrade to PowerPC 440 and use the SecureIP simulation library, or try using SmartModel for PowerPC 405 from ISE 10.x as described in the currect article.


The Virtex-II Pro, Virtex-4 and Virtex-5 families are the platform FPGA devices for designs that employ IP cores and customized modules. The family incorporates RocketIO, PowerPC CPU, Ethernet MAC cores, etc. in the FPGA architecture. SmartModels are an encrypted version to the actual HDL code. These models allow you to simulate the actual functionality with no access to the code itself. A simulation of these new features requires the use of Synopsys SmartModels along with the user design. This application note will show you how to install, use, and simulate these models in Aldec’s Active-HDL software.

Installing PowerPC and Rocket I/O SmartModels

Xilinx's ISE package (10.x or earlier) contains the SmartModels that allow simulation of Rocket IO, PowerPC CPU and Ethernet MAC. In order to install the SmartModels libraries, follow the instructions below.

  1. Launch the SmartModel Library Installer from your Xilinx ISE 10.x (or earlier) installation folder. The executable file sl_admin.exe can be located at: %XILINX%\smartmodel\nt\image\pcnt\sl_admin.exe

    NOTE: %XILINX% is an environment variable pointing to the Xilinx ISE installation directory. The default value is C:\Xilinx.

  2. Use the Install option from the Actions menu or the Install icon located on the left-hand side of the window (Figure 1).

    Figure 1.

  3. In the Install From... dialog window, point to:


    Figure 2.

  4. The Select Models to Install window will appear. Select Add All and then click on OK (Figure 3).

    Figure 3.

  5. In the next dialog, the Wintel check box should be selected. Check Cadence Design Systems and Other in the EDAV Packages section (Figure 4).

    Figure 4.

  6. Press the OK button to install the RocketIO, PowerPC, and Ethernet MAC SmartModel libraries (Figure 5)

    Figure 5.

Make sure that the LMC_HOME environment variable is properly set to:


Instantiating PowerPC, Rocket I/O and Ethernet MAC

You can instantiate the PowerPC, Rocket I/O, or Ethernet MAC design units directly in your HDL code. Active-HDL comes with precompiled and ready-to-use Xilinx unisim library containing both Verilog and VHDL wrappers for the respective SmartModels.

Instantiation in a VHDL Source Code

Add Xilinx unisim library declaration and the use clause to your code where you plan to instantiate a SmartModel.

library UNISIM;
use UNISIM.vcomponents.all;

Instantiation in a Verilog Source Code

Add Xilinx ovi_unisim library to the list of Verilog Libraries in Verilog compilation options window (Figure 6)

Figure 6.

If you are running simulations in the batch mode or using the .do files, you should add -l ovi_unisim switch to your alog/vlog command.

NOTE: Precompiled Xilinx unisim and ovi_unisim libraries can be downloaded from Active-HDL download web page or upon your login to your support account at It is assumed that this library is mapped as global using the command below:

vmap global ovi_unisim <path_to_ovi_unisim_dir >

Building the swift_lmtv Library

This library is not delivered with Active-HDL and must be built by the user. The library is required only for simulation with LMTV SmartModels. Other models from the SmartModel library can use the (Solaris, Linux) or swift.dll (Windows) library included in the installation package. Building the libwift library requires files both from the Active-HDL installation directory and the SmartModel library. It is assumed that the required files from the SmartModel library will be copied to the interfaces/synopsys subdirectory of Active-HDL. Additionally, the $VSIMSACFG variable must be set in order for the compiler to find the include files in the PLI/Include directory of Active-HDL. Building the library requires gnu make and the gcc compiler that are available as the part of Active-HDL installation.

To build the library follow the instructions in readme.txt file located in <Active-HDL/interfaces/synopsys/swift_lmtv> directory. If the build process is succeessfull, the following message is printed to the console:

-= Library `' built successfully =-

Simulating the Design

For the Verilog designs add a path to either swift.dll/so or swift_lmtv.dll/so in the list of PLI applications in the Verilog tab of the Simulation options dialog box in Active-HDL GUI. Note that it is not recommended to enable both libraries (swift.dll and swift_lmtv.dll) in the PLI Application setting if LMTV SmartModels are used. Specifying both libraries may cause problems while simulating LMTV models. Use –pli switch with asim command if you are using a macro or a script for running the simulation.

VHDL designs will use that comes in Active-HDL’s BIN directory. No special action is required from a user.

During the initialization and simulation run, messages generated in the Console window indicate the status of the instantiated SmartModel units:

# : SWIFT: Beginning the session.
# : Copyright (c) 1984-2005 Synopsys Inc. ALL RIGHTS RESERVED
# : You can use the Browser tool to configure the SmartModel
# : Library and access information about SmartModels:
# :    $LMC_HOME/bin/sl_browser
# :
# : SmartModel product documentation is available here:
# :    $LMC_HOME/doc/smartmodel/manuals/intro.pdf
# :
# :
# : Model gt_swift: Model Vendor: `Xilinx'.
# :  at time: 0[fs]
# : SWIFT: Model instance blockdiagram7.U1.GT_inst.gt_swift_bw_1.gt_swift_inst(gt_swift) initialized.

Controlling the SmartModels

Active-HDL provides several commands that allow controlling the SmartModels during the simulation via so-called Command Channel:

  • sm_cmd

  • sm_session_cmd

  • sm_reset

  • sm_win

  • sm_prepare

Please, refer to the Active-HDL on-line documentation and the Synopsys SmartModel manual for more information about the syntax and use of the commands mentioned above.

Accessing Internal Registers of PowerPC Processor Model

Synopsys SmartModels are equipped with a mechanism that allows the user to read, write, and reset internal objects. This capability is called SmartModel Windows. Active-HDL provides several commands that allow users either to write or read the contents of a Window:

  • sm_win;

  • sm_reset.

Writable windows are not supported in the PowerPC model of Xilinx, so the following example will show you how to read the values stored in the internal registers of the processor.

In certain models, a window has to be enabled before it can be read. The Xilinx PPC405 model also needs to be initialized in this way:

sm_win enable <hierarchy_path>/<register_name> >

where <hierarchy_path > is the full path in the design hierarchy to the PPC405_swift_inst unit, while <register_name > is the name of the register that you want to read e.g.

sm_win enable /U1/IPPC405_SWIFT/PPC405_swift_inst/GPR0 >

Then issue the following DO macro command in the Console window or your simulation script to read the General Purpose Register GPR0 of the /U1/IPPC405_SWIFT/PPC405_swift_inst instance:

sm_win read /U1/IPPC405_SWIFT/PPC405_swift_inst/GPR0 >

As a result, you should see the values returned from the simulated model:

# : SWI FT: Value of register GPR0 of model 0 is : 11111111111111111110000001011000

Continuous Monitoring of Internal Registers in Waveform Viewer

Active-HDL provides procedures that allow continuous reading of the internal registers. The contents of the internal model registers are mapped to signals and thus can be observed in the Waveform Viewer.

Mapping registers in VHDL

The Aldec library installed with Active-HDLc contains the sm_win_pkg package storing the declaration of the ready-to-use foreign procedure map_window_signal. It allows continuous reading of the internal registers in VHDL designs. To use the map_window_signal procedure, insert the following declaration in your code:

library aldec;
use aldec.sm_win_pkg.all;

To map GPR0 used in the previous examples to the win_GPR0 signal, use the following procedure call:

map_window_signal( "win_GPR0", "/U1/IPPC405_SWIFT/PPC405_swift_inst/GPR0"); The win_GPR0 signal will follow changes on the GPR0 register of /U1/IPPC405_SWIFT/PPC405_swift_inst instance.

Mapping registers in Verilog

To copy the contents of SmartModel registers to Verilog regs the $lm_mapsignal task can be used. The syntax of the task is as follows:

$lm_mapsignal("<signal name>", "<window instance>");

The $lm_mapsignal task is provided in the swift.dll library. Before it can be used, you should add the swift.dll library to the list of PLI application in the Simulation Options | Verilog window.

Reading the internal registers by using the $lm_mapsignal task is not available if the model requires the swift.dll library.

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