Want to be a Verification Engineer? Practice. Practice. Practice.

Simulate UVM & SystemVerilog online for free

Victor Lyuboslavsky, CEO at Victor EDA, Inc.
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HDL design and verification engineers are being absorbed by the job market faster than universities can create them. The desperation of high tech firms is evident in aggressive job posts offering paid relocation, bonuses and other incentives. You may have found yourself among those eyeing the job market and wondering, “How hard is it to switch fields and become a verification engineer?”

It can be difficult, as it turns out. 

But it can be done if you are committed to following the steps:


1. Learn the basics of HDL design and verification. This part is fairly straightforward and can be picked up from books and web resources.


2. Practice. It’s vital to actually “do the work” so that you are able to answer hands-on interview questions. Unfortunately, it is surprisingly difficult to practice simulating UVM and SystemVerilog unless you have access to university licenses, are already working for a semiconductor company, or are fortunate enough to have a high-level friend at one of the simulator vendors.


3. Join a community. To give you a competitive edge it is important to become part of a community of like-minded engineers, who are willing to help each other out without a corporate agenda.


Not long ago, I myself was preparing for job interviews and working to ramp up on SystemVerilog and UVM. I used the web to find code examples and tutorials. However, the examples were often incomplete. Occasionally they were missing the necessary code to hook the example into a real design. Other times, the code examples had syntax errors - I might be presented with a supposedly working design, with lines stripped out, but with undefined variables and dangling commas left in. Other times the code examples simply did not work on my simulator. The result was endless frustration for the student in me.


I knew there had to be a better way, so I created EDA Playground.


Now, for the first time ever, students, hobbyists and engineers from all over the globe have access to run and share full SystemVerilog code from their own web browser.


EDA Playground is a free web application that allows users to edit, simulate (and view waveforms), synthesize, and share HDL code. Its purpose is to accelerate the learning of design and testbench development with easier code sharing and simpler access to simulators and libraries. EDA Playground is specifically designed for small prototypes and examples, and is not intended to be used for a full-blown FPGA or ASIC design.


The usage model is simple: type in your code, select a simulator/synthesis tool, and click run. If your simulation dumps waves, simply click a checkbox and the waves will open in a new window after the run. Any code or waveform display may be saved as a static HTML link (like this UVM Hello World example) enabling anyone to open up the code, re-run it, and get the same result.



Fig. 1 EDA Playground in action


Currently, one of the tools available on EDA Playground is a limited version of Aldec® Riviera-PRO™, which supports SystemVerilog or VHDL. Supported verification libraries include UVM, OVM, OVL, and SVUnit. Additional features, such as coverage reports, SystemC support, and others are coming soon.


Example Use Cases for EDA Playground


Remember I mentioned it is helpful to have a community of like-minded engineers to help each other out? It turns out that StackOverflow fits this criteria. It is a popular technical question and answer forum where users gain reputation for good questions and answers. It already has over 100 questions and answers with links to code on EDA Playground, and growing. This is where I turn for my own HDL and verification coding questions.


EDA Playground can be used for training, but several companies are also using it to test candidates’ hands-on coding skills. EDA Playground’s collaboration mode allows two or more individuals to view and edit code at the same time. This is especially useful during phone interviews, where hiring managers can send a collaboration link to the candidate, and then watch as the interviewee creates a testbench or debugs real code.


Most of EDA Playground’s 5,000+ users are leveraging the free application for quick prototyping or simply playing around and trying something out. It is a playground, after all. I hope you’ll visit and jump in today. If you want to learn more, you’ll find the EDA Playground YouTube channel with over 35,000 views to-date is a great place to start.



Victor Lyuboslavsky has over 15 years of experience in high tech. He has worked in HDL design and verification, PCB design, semiconductor physical design, and software development. In 2013, he founded Victor EDA, Inc. to provide web-based tools to design and verification engineers. Victor EDA aims to bring the best software development practices to the semiconductor design and verification community.

  • Products:
  • Riviera-PRO
  • Advanced Verification


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