Resources

Due to the size and complexity of current hardware design, design verification tasks can become increasingly complex and lengthy. Recent advancements in hardware design have focused on cleaning up design code as much as possible prior to entering the design verification stage. Unfortunately, such design code cleanup performed during relatively short time may significantly reduce overall design verification time and effort. As SystemVerilog design constructs gain popularity among hardware designers, it is increasingly important to assist designers with Systemverilog design code verification and cleanup. ALINT-PRO™ is a design verification solution for SystemVerilog, Verilog and VHDL RTL code. It is able to statically verify and cleanup the code far beyond compiler-level checks. It is capable of statically verifying most of the popular SystemVerilog design constructs, uncovering some of critical design issues early in the design cycle.  Play webinar   

Advanced Driver Assistance Systems (ADAS) provide a significant contribution to increasing automotive safety. ADAS systems provide the driver with increased situational awareness, helping to reduce collision and accidents. To provide the driver with increased situation awareness ADAS systems can be categorized as providing external or internal awareness. External ADAS systems monitor such aspects as blind spots and lane detection, while internal systems monitor the occupants and particularly the driver themselves such as Driver Drowsiness Detection. Both internal and external ADAS systems rely heavily upon embedded vision systems, implementing these embedded vision systems depending upon the task at hand can be computationally intensive. This computational complexity can reduce the performance of the system introducing latency and reducing the validity of the information provided to the driver. The use of hardware programmable logic enables the implementation of a low latency high performance system. However, industry standard development techniques such as the use of OpenCV cannot be used due to high development cost and timescales. This webinar will demonstrate how an ADAS driver drowsiness detection application can be implemented using a Zynq heterogeneous SoC which combines programmable logic with high performance ARM cores. This example will demonstrate how a System Optimizing Compiler can be used in conjunction with the Zynq to create the ADAS application using high level languages and industry standard frameworks. The use of the System Optimizing Compiler enables seamless acceleration of C functions into the programmable logic, enabling a significant performance increase.  Play webinar   

Finite State Machines (FSM) are a key part of safety-critical design control logic. During the operation of the FPGAs within the systems, single-event upsets or other radiation effects can cause the internal logic to flip to an incorrect value from ‘0’ to ‘1’ or ‘1’ to ‘0’ in a non-deterministic way, causing the system to fail. As transistors shrink, errors are becoming much more common; in a modern chip the devices are so small that cosmic rays or alpha particles can change the value of bits that are stored in FSM registers. In this webinar we will provide the various methods on how to develop robust and safe FSMs - from best practices in FSM design to highly reliable FSM design methods , allowing designers to develop state machines with transient errors detection and correction. Play webinar   

Universal Verification Methodology (UVM) is one of the most popular approaches in using transactional testbench environment. The growth of SoC designs forces design and verification teams to use emulation as a way to speed-up verification process. Standard CoEmulation Modeling Interface (SCE-MI) provides ways to connect emulated design with transactional testbench. This paper describes how to use SCE-MI to create UVM test environment that is ready for both simulation and emulation.

Hardware Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design. Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module. Play webinar   

Cocotb is a CO-routine based CO-simulation Testbench environment for verifying VHDL/Verilog RTL using Python. It is an open-source environment and hosted on Github. . It uses the same design-reuse and functional verification concepts like UVM, however is implemented in Python. In this webinar, we will introduce Cocotb, and will outline how Cocotb can provide significant savings in development time, promote code re-use and ultimately reduce project time-to-market and total development cost.  Play webinar   

Presenter: Sergei Zaychenko, Aldec Software Product Manager

Noise reduction is a key trend in currently available Clock Domain Crossing (CDC) Verification solutions. Most CDC tools on the market are unable to extract clocking and reset structures that match the original designer's intent. The designs often contain hundreds of vendor-specific blocks and 3rd-party IPs with unclear clock/reset relations. The timing of external interfaces might not be clearly defined, affecting the CDC results. Multiple clock modes, false paths and custom in-house synchronizers are not making CDC analysis any easier.

A user must typically go through several rounds of tool configuration, policy adjustments, clock/reset constraints refinements, description of timing intent for the black boxes. Bringing the focus to concrete configuration/constraint issues is challenging when forced to browse through thousands of violation messages and full schematics. Much time and effort might be lost on cleaning the configuration through printed CDC end-results, instead of keeping initial focus on correct control structures. In additional, an incorrect/incomplete configuration often leads to poor CDC tool performance.

In this webinar, learn how a seamless, phased-based CDC debugging methodology can reduce overall CDC signoff time.  Play webinar   

Abstract: The main purpose of DO-254 Verification Process (Chapter 6.2 of DO-254 Specification) is not merely to verify the functionality of the design but more importantly to obtain assurance that the hardware implementation meets the requirements defined in the early stages of DO-254 targeted project. It is absolutely critical to ensure that the same requirements are preserved in all stages of design and verification from planning to hardware testing. Learn in this webinar an effective approach to verifying your design from the RTL to hardware preserving the same requirements. Our experts will teach you how to use Assertions and Code Coverage for a systematic and comprehensive verification. Our experts will also demonstrate the advantages of component level verification with DO-254 CTS (Compliance Tool Set) ideal to hardware verification of Level A/B DO-254 designs. Play webinar   

Abstract: With the complexity of some FPGA designs now comparable to ASIC, designers are faced with challenging cost, power and functional goals. Leading-edge FPGA designs will now benefit from advanced verification methodologies, but do ASIC-focused EDA vendors offer the best solution? This webinar will explain how Aldec tools are uniquely positioned to efficiently support the verification of complex FPGA designs and how (in combination with the new devices from Lattice) designers can meet their functional, cost and power requirements for complex high volume applications. Play webinar   

Appendix B of RTCA DO-254 describes elemental analysis as one of the possible additional verification techniques for Level A and B complex electronic hardware. Code coverage in and of itself does not always satisfy the objectives of DO-254. This presentation provides background on elemental analysis and when code coverage is sufficient for HDL based designs. The discussion will cover the various types of code coverage and which ones are relevant to certification authorities. Suggestions for resolving coverage holes will also be discussed. Play webinar   

In this webinar, we’ll discuss typical synchronizer structures to put in place for CDC crossings as well as the most common mistakes in their structure. We’ll also cover some of the functional problems that often arise due to incorrect synchronization, as well as how to verify a project against CDC issues during the RTL design and RTL simulation design stages. Play webinar