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Title: VHDL testbenches using models, scoreboards and transactions

Description: The European Space Agency’s UVVM extension project is continuously adding more functionality to the open source UVVM – to improve the FPGA verification efficiency and design quality on deliveries to the space industry. This is of course equally important for the electronics industry in general. UVVM is unique when it comes to testbench overview, readability, maintainability, extensibility and reuse; - all the important factors for efficiency and quality – independent of methodology and language. Last summer the ESA project provided a generic Scoreboard with lots of user-friendly functionality. The basic task of such a Scoreboard is to check actual data out of a DUT (Device Under Test) and compare this to the expected data. The scoreboard typically also allows flexibility in the comparisons and provides good statistics. The expected data typically come from a file (e.g. generated from a high-level tool like Matlab) or from some functionality inside the testbench. In the latter case it is quite common that the test sequencer generates both the stimuli and the expected response as it executes the test case, but it is often better and more structured to have a separate model handling the generation of the expected output. This way the test sequencer will be simpler and the total testbench overview improve. This webinar will give an introduction to Scoreboards and show a complete advanced testbench environment, test harness and test sequencer – using verification components, BFMs, scoreboard and a simple behavioral model. The test harness and test sequencer will be explained, and a demo will be simulated in order to show the basic usage and functionality of the Scoreboard and the model. The presentation will also show how UVVM significantly simplifies VHDL verification, provides overview and readability, and allows very efficient reuse. The benefits of standardized verification components will be easy to see from this demo.

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