Play Webinar

Title: Making a Simple, Structured and Efficient VHDL Testbench

Description: Guest Presenter: Espen Tallaksen - Bitvis CEO and Principal FPGA/ASIC Developer

Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. They often take far too much time to implement and provide close to no support when debugging potential problems. This webinar will demonstrate how to build a far better testbench with respect to all these issues - in significantly less time. The webinar will also explain how this verification approach results in reduced design and debug time with the help of an open-source testbench infrastructure library.

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