Play WebinarTitle: Making a Simple, Structured and Efficient VHDL TestbenchDescription: Guest Presenter: Espen Tallaksen - Bitvis CEO and Principal FPGA/ASIC Developer Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. They often take far too much time to implement and provide close to no support when debugging potential problems. This webinar will demonstrate how to build a far better testbench with respect to all these issues - in significantly less time. The webinar will also explain how this verification approach results in reduced design and debug time with the help of an open-source testbench infrastructure library.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
