Play Webinar

Title: FPGA Verification with VHDL and UVVM Part 1: New Features and Best Practices

Description: Riviera-PRO includes a pre-compiled version of the latest UVVM, providing users with direct access to a robust verification methodology for VHDL designs. This latest version introduces significant new features, including Completion Detection and Detection of Unwanted Activity, further enhancing verification accuracy and reliability. UVVM simplifies the creation of VHDL testbenches and test sequencers, making them easy to write and understand — even for complex Devices Under Test (DUTs). Just as a well-structured (good) architecture is critical for FPGA design, it is equally essential for verifying complex designs. An effective verification architecture directly impacts efficiency and product quality. By adopting UVVM, teams can save hundreds of hours and reduce the number of design iterations significantly. Developed in close collaboration with the European Space Agency (ESA), UVVM extensions are specifically designed to meet these goals, ensuring robust and efficient verification. In this webinar, we will cover the fundamentals of UVVM, explore various features that enhance quality and productivity, and take a closer look at the latest enhancements introduced in this version

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