Starting Active-HDL as Default Simulator in Xilinx Vivado 2017.4 or Later

Introduction

This document describes how to start the Active-HDL simulator from Xilinx Vivado™ to run behavioral and timing simulations. This application note has been verified on Active-HDL 10.5, Xilinx Vivado 2017.4, and the Active-HDL Simulator 1.13 add-on to Vivado. This integration allows users to run VHDL, Verilog, Mixed, and SystemVerilog (Design) simulations using Active-HDL as the default simulator.

Setting up Active-HDL Add-on

  1. Set the path to the Active-HDL installation directory in the 3rd Party Simulators category of the Settings window that can be invoked from the Flow Navigator pane of Vivado. Alternatively, add the Active-HDL installation directory to the PATH environment variable. The settings from the Vivado environment take precedence over the path specified in the environment variable.

    NOTE: If Vivado is already running while you modify the PATH environment variable, then you will have to restart Vivado to have your new PATH variable effective inside Vivado.

  2. Select the Xilinx Tcl Store option from the Tools menu, switch to the Installed tab, and make sure that the Active-HDL Simulator plug-in is already installed. If it is not, find the plug-in under the All tab and click the Install button. If the plug-in is already installed, you can update it to the latest version with the Refresh button.

Installing Xilinx libraries in Active-HDL

In order to run the simulation successfully, depending on the design, both VHDL and Verilog simulation libraries for the respective Xilinx Vivado version may have to be installed in Active-HDL. You can check which libraries are currently installed in your Active-HDL version using the Library Manager tool. The tool can be accessed by selecting the Library Manager option from the View menu. Libraries have to be compiled for the Active-HDL version you are using for simulation.

You can obtain libraries in multiple ways:

  1. You can compile Xilinx libraries from sources with the compile_simlib -simulator activehdl command of Vivado.

    NOTE: After generating the compiled libraries from Xilinx, they have to be manually attached to Active-HDL. For more information refer to Compiling Xilinx Vivado Simulation Libraries for Active-HDL.

    You can also install precompiled libraries:

  2. If you have received a web link to download Active-HDL, on the same page you will find the links to download Xilinx libraries.

  3. At any time you can visit the Update Center to download the latest Xilinx libraries at http://www.aldec.com/en/downloads.

Here is the typical sequence you would like to follow to run Active-HDL from Vivado:

  1. Create or Open a project in Xilinx Vivado Project Manager.

  2. Select the Settings tab from the Flow Navigator pane.

  3. Under the Simulation category of the Settings window, change the Target Simulator to Active-HDL Simulator.

  4. The libraries used in the project should be specified either in the Active-HDL or Vivado environments. To do so, set the libraries as global in the Library Manager window of Active-HDL. Alternatively, specify the path to the library.cfg file associated with the required libraries in the Compiled library location field.

  5. Here under the Compilation tab, you can pass arguments to the Verilog and VHDL compiler.

    NOTE: You may need to select the activehdl.compile.vhdl_relax check box that relaxes some LRM requirements when compiling VHDL files.

  6. Under the Elaboration and Simulation tabs you can set simulation related arguments e.g. logging all signals to simulation database, accessing signals for waveform, simulation run time.

  7. Once all options are set according to your requirements, click OK.

    NOTE: If a version of Active-HDL was updated between subsequent simulation runs, you should clear the Enable incremental compilation option available in the Advanced tab of the Simulation category to remove the files compiled with previous version of Active-HDL.

  8. Now, click on the Run Simulation item in the Flow Navigator pane and select the type of simulation you want to run.

  9. Vivado generates DO macro scripts for compilation and simulation based upon the settings you provided in the above steps.

  10. The Aldec's compiler is launched in the command line mode and the compilation macro is executed. The compiler output is redirected to the Vivado Tcl Console window.

  11. If compilation is finished successfully, Active-HDL is launched and the simulation macro is executed. The macro creates a design, adds all the source files into it and initializes simulation. The simulation results are then presented in the waveform window. At that point, you can navigate through the history of the console window using the arrows keys and relaunch any command from the simulation macro.

export_simulation command

The export_simulation command allows you to export the compilation and simulation macros generated by Vivado to the directory specified with the -run_dir argument. The macro to be exported is denoted with the -mode and -type arguments.

Syntax

tclapp::aldec::activehdl::export_simulation -run_dir [-lib_map_path] [-mode] [-type] [-quiet] [-verbose]

Arguments

-run_dir

Specifies the directory to which the macros selected with the -mode and -type arguments will be exported.

-lib_map_path

Specifies the directory containing the precompiled simulation library.

-mode

Sets the simulation mode. The following modes are allowed: Behavioral, Post-synthesis, and Post-implementation that can be selected with the behavioral, post-synthesis, and post-implementation parameters, respectively.

-type

Specifies the netlist type. The allowed values are functional and timing. This argument is only applicable when the selected simulation mode is Post-synthesis or Post-implementation (post-synthesis or post-implementation passed to -mode).

-quiet

Suspends displaying of error messages reported by the command.

-verbose

Suspends limiting of messages displayed in the console during the command execution.

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