Using ALINT with Aldec and Third-Party Simulators

Overview

ALINT is a design rule checking environment that can be used in a stand-alone fashion or with any other simulator. You can use ALINT at any level during design development just like simulator – this document explains typical use scenarios:

  1. ALINT + Aldec Riviera-PRO

  2. ALINT + Aldec Active-HDL

  3. ALINT + Third-Party Simulator

Starting the Tool

ALINT can be started either in the GUI or batch mode:

GUI mode – go to installation directory and run the runalint script (.bat – Windows, .sh – Linux).

Batch mode

  • runalintcon (located at $alint_install_dir) – interactive mode

  • vlint (located at $alint_install_dir/bin) – non-interactive

Figure 1: ALINT Default User Interface

Assuming that you have a valid license, the User Interface should look like as shown in Figure 1 (Quick Launch Panel and a few preconfigured perspectives are available). Perspectives allow changing the GUI layout quickly while switching between different tasks.

To start working with ALINT GUI it is necessary to create a new design or open an existing one. A Design is a collection of individual files (HDL source files, macros, scripts, etc). It allows grouping and working with a number of files stored even in different locations or shared with other designs. Once you collect all design files, you can add, modify, save, or remove them from an active design, compile sources, execute macros and scripts. ALINT is capable of Verilog and VHDL design rule checking – files of any other formats are not officially supported by the tool and need to be converted to either Verilog or VHDL before importing.

Scenario #1 – ALINT and Aldec Riviera-PRO

Designs from Riviera-PRO can be directly used in ALINT environment. To open your Riviera-PRO design in ALINT you should do the following:

  1. Select the Design option from the File | Open menu and browse to the location where you have saved your Riviera-PRO design. Select the .rdsn file and click open. The design will be added to the current workspace (workspace will be created automatically if it did not exist).

  2. If your workspace has multiple designs then make sure that added design is set as an active design. If not then right click on the design and set the newly added design as active design.

  3. Exclude SystemVerilog and C++ files, if any, from the linting process using the Compilation Without Linting option in the Design Manager right-click menu.

  4. Associate a design with linting flow – create a new flow based on template (e.g. ALDEC_Chapters) using the File | New | Flow… menu item.

Once you are done with design opening, you can add FPGA vendor libraries if your design uses any.

Similar versions of Riviera-PRO and ALINT – if you have similar versions (e.g. Riviera-PRO 2010.06 and ALINT 2010.06) then the following steps must be performed to attach a precompiled library:

  1. Click the Attach Library button in the Library Manager.

  2. Type a new library name in the appropriate edit box.

  3. Point the tool to a pre-compiled library file (.lib).

Different versions of Riviera-PRO and ALINT – if you have different versions (e.g. Riviera-PRO 2012.02 and ALINT 2012.01) then the following steps must be performed to attach a precompiled library:

  1. Copy the library files (.lib and .mgf) to a convenient location (e.g. $alint_install_dir/vlib/new_lib_name). The precompiled libraries are available for download from our Support Portal.

  2. Click the Attach Library button in the Library Manager.

  3. Select the appropriate .lib file and click the OK button.

  4. Select the Toggle Read Write option if there is the (RO) sign after the library name.

  5. Click the Refresh button in the library right-click menu. Some libraries may depend on other libraries – compilation errors may occur in such cases – dependent libraries can be refreshed only after adding the base ones (e.g. cycloneiv_hssi depends on sgate which depends on lpm а in order make the components from cycloneiv_hssi available you will have to add all mentioned libraries and refresh them in the following order: lpm, sgate, cycloneiv_hssi).

  6. (Optional). Use the Make Library Global option from the library right-click menu if a recently added library is reused extensively between your designs – once a library is set as global it becomes automatically available in all ALINT designs.

Scenario #2 – ALINT and Aldec Active-HDL

In order to use Active-HDL designs with ALINT, project source files need to be imported manually. To import your Active-HDL design to ALINT you should do the following:

  1. From the File | New menu open the Design... option. The Create New Design Wizard will be opened.

  2. Type in design name.

  3. Select location for design directory (use the Browse button to point the desired location). If you want to create additional directory for design – check in appropriate checkbox.

  4. Make sure that linting flow template is selected (e.g. ALDEC_Chapters).

  5. Click the Finish button. Design will be created in the pointed directory.

  6. Add Verilog and VHDL source files to the newly created design (right click the design and select Add | Existing File menu item).

Note – Block (.bde) and State (.asf) Diagram sources are not directly supported by ALINT – their HDL equivalents must be imported instead. When you compile BDE and FSM files in Active-HDL, it generates HDL files and stores them in the compile folder inside your active design.

You should refer to the Library Manager if your design uses any vendor libraries – the following steps must be performed to attach an Active-HDL library to ALINT:

  1. Copy the library files (.lib and .mgf) to a convenient location (e.g. $alint_install_dir/vlib/new_lib_name).

  2. Click the Attach Library button in the Library Manager.

  3. Select the appropriate .lib file and click the OK button.

  4. Select the Toggle Read Write option if there is the (RO) sign after the library name.

  5. Click the Refresh button in the library right-click menu.

  6. (Optional). Use the Make Library Global option from the library right-click menu if a recently added library is reused extensively between your designs – once a library is set as global it becomes automatically available in all ALINT designs.

Scenario #3 – ALINT and Third-Party Simulator

This section describes how to quickly set up a design and import necessary HDL files in ALINT if you are using a third-party simulator or ALINT only.

Importing project source files with Design Creation Wizard (recommended) – to create a new design you should do the following:

  1. From the File | New menu open the Design... option. The Create New Design Wizard will be opened.

  2. Type in design name.

  3. Select location for design directory (use the Browse button to point the desired location).

  4. Make sure that linting flow template is selected (e.g. ALDEC_Chapters).

  5. Click the Finish button. Design will be created in the pointed directory.

  6. Add the source files to the newly created design (right click the design and select Add | Existing File menu item).

Importing project source files with quick design creation button – another way to quickly create a design (add the source files automatically):

  1. Switch to Default perspective or manually open the File Browser (Alt +3).

  2. Right-click on the source file folder from the File Browser window.

  3. From the context menu select the Create Design item:

  4. Newly created design can be observed in the Design Manager. A design is not assigned with any linting flow by default when it is created automatically (quick design creation button) – you can use the Flow Creation Wizard at File | New | Flow… to create a custom flow from template.

If you need to add any FPGA library and don’t have a .lib file that contains pre-compiled version of this library then you must compile the library from the source files. The following set of macro commands creates the my_lib library from the source files listed in the library_vhdl_files_list.txt and library_vlog_files_list.txt files:

alib my_lib
# VHDL files:
acom -work my_lib -f library_vhdl_files_list.txt

or

# Verilog files:
alog -work my_lib -f library_vlog_files_list.txt

And if you already have the pre-compiled library then the following steps must be performed to attach it:

  1. Click the Attach Library button in the Library Manager.

  2. Type a new library name in the appropriate edit box.

  3. Point the tool to a pre-compiled library file (.lib).

  4. Click the Refresh button in the library right-click menu.

Refining Design

Once your design is imported and all the necessary libraries are set up, you are ready to go.

ALINT designs contain links to the actual source files – this means that every source file change appears in the original design immediately and updated source file is ready for simulation at any time. You basically can keep both your simulator and ALINT open and switch between them whenever it is necessary – regardless of the simulator you use.

You have two approaches to the design analysis and refinement process – traditional and Phase-Based Linting (PBL) methodology. We recommend using the PBL methodology whenever possible – search our Knowledge Base for “Phase-Based Linting Methodology” to get more information on this.

Once you select a flow, just go to the Flow Manager, click the Run button and go through the step-by-step process of fixing violations at every phase. To analyze a phase execution results, right-click the phase and select the View Stage Results item from the dropdown menu to review the results of this phase – dedicated Violation Viewer (Figure 2) allows convenient linting results navigation and analysis.

Figure 2: Violation Viewer

The Violation Viewer can be used for the following key things:

  1. Analyzing detected design issues from different viewpoints (sources, design units, instances, etc).

  2. Narrowing the results according to any custom criteria (filters).

  3. Exporting to other formats (.html, .csv, .txt).

  4. Cross-probing with the source code (quick jump to description that causes a rule violation).

  5. Setting violation statuses (e.g. fixed, irrelevant, etc)

Figure 3: Design Refinement Flow with ALINT

Quick context-dependent reference is available in the Rule Description Viewer once a rule violation is selected in the Violation Viewer. It gives useful information about currently addressed rule (quick explanation, example, and workaround).

Summary

You can easily use ALINT with any simulator or as a standalone application – it typically requires you to:

  1. Create a design and add the source files.

  2. Add vendor libraries, if any, and select a linting flow.

  3. Run analysis and refine the design.

Applies To:

  • ALINT 2012 Windows

  • ALINT 2012 Linux

Ask Us a Question
x

Ask Us a Question

x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.