DO-254 Verilog / VHDLルール・ライブラリ

Category : デザイン・ルール・チェック

Set of rules that should be used to improve design compliance with DO-254. It combines knowledge of Aldec’s DO-254 clients and in-house experts. Covered areas include proper signal assignments, clocks/resets issues, correct instantiations, handling of race conditions and mismatched bit widths.

Ask Us a Question
x
Ask Us a Question
x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.